Anatomy of 2D materials based memristors: the role of each type of defect

dc.conference.dateNovember 7-8,2022
dc.conference.locationTHUWAL, SAUDI ARABIA
dc.conference.namePSE Annual Research Expo
dc.contributor.authorShen, Yaqing
dc.date.accessioned2022-11-03T07:28:48Z
dc.date.available2022-11-03T07:28:48Z
dc.date.issued2022-11-07
dc.description.abstractIn the race of fabricating solid-state nano/micro-electronic devices using two-dimensional (2D) layered materials (LMs), achieving high yield and low device-to-device variability are the two main challenges. Electronic devices that drive currents in-plane along the 2D-LMs (i.e. transistors, memtransistors) are strongly affected by local defects (i.e. grain boundaries, wrinkles, thickness fluctuations, polymer residues), as they create inhomogeneities and increase the device-to-device variability, resulting in a poor performance at the circuit level. Here we show that memristors are insensitive to most types of defects in 2D-LMs, even when fabricated in academic laboratories that do not meet industrial standards. The reason is that the currents produced in these devices, which flow out-of-plane across the 2D-LM, are always driven locally by the most conductive locations. Consequently, we conclude that it is much easier to fabricate 2D-LMs based solid-state nano/micro-electronic circuits using memristors than transistors or memtransistors, not only due to the inherent simpler fabrication process (i.e. less lithography steps), but also because the local defects do not degrade the yield and variability of memristors considerably.
dc.identifier.urihttp://hdl.handle.net/10754/685400
dc.titleAnatomy of 2D materials based memristors: the role of each type of defect
dc.typePoster
display.details.left<span><h5>Type</h5>Poster<br><br><h5>Authors</h5><a href="https://repository.kaust.edu.sa/search?spc.sf=dc.date.issued&spc.sd=DESC&f.author=Shen, Yaqing,equals">Shen, Yaqing</a><br><br><h5>Date</h5>2022-11-07</span>
display.details.right<span><h5>Abstract</h5>In the race of fabricating solid-state nano/micro-electronic devices using two-dimensional (2D) layered materials (LMs), achieving high yield and low device-to-device variability are the two main challenges. Electronic devices that drive currents in-plane along the 2D-LMs (i.e. transistors, memtransistors) are strongly affected by local defects (i.e. grain boundaries, wrinkles, thickness fluctuations, polymer residues), as they create inhomogeneities and increase the device-to-device variability, resulting in a poor performance at the circuit level. Here we show that memristors are insensitive to most types of defects in 2D-LMs, even when fabricated in academic laboratories that do not meet industrial standards. The reason is that the currents produced in these devices, which flow out-of-plane across the 2D-LM, are always driven locally by the most conductive locations. Consequently, we conclude that it is much easier to fabricate 2D-LMs based solid-state nano/micro-electronic circuits using memristors than transistors or memtransistors, not only due to the inherent simpler fabrication process (i.e. less lithography steps), but also because the local defects do not degrade the yield and variability of memristors considerably.<br><br><h5>Conference/Event Name</h5><a href="https://repository.kaust.edu.sa/search?spc.sf=dc.date.issued&spc.sd=DESC&f.conference=PSE Annual Research Expo,equals">PSE Annual Research Expo</a></span>
refterms.dateFOA2022-11-09T06:22:06Z
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