Experimental verification of on-chip CMOS fractional-order capacitor emulators

Type
Article

Authors
Tsirimokou, G.
Psychalinos, C.
Salama, Khaled N.
Elwakil, A.S.

KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program

Online Publication Date
2016-06-13

Print Publication Date
2016-07-21

Date
2016-06-13

Abstract
The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.

Citation
Tsirimokou G, Psychalinos C, Salama KN, Elwakil AS (2016) Experimental verification of on-chip CMOS fractional-order capacitor emulators. Electronics Letters 52: 1298–1300. Available: http://dx.doi.org/10.1049/el.2016.1457.

Publisher
Institution of Engineering and Technology (IET)

Journal
Electronics Letters

DOI
10.1049/el.2016.1457

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