An independent component analysis (ICA) has been used in many applications, including self-interference cancellation (SIC) for in-band full-duplex (IBFD) wireless systems and anomaly detection in industrial Internet of Things (IoT). This article presents a high-throughput and highly efficient configurable preprocessing accelerator for the ICA algorithm. The proposed ICA accelerator has three major blocks that perform data centering, covariance matrix for computation, and eigenvalue decomposition (EVD). Specifically, the proposed accelerator is based on a high-performance matrix multiplication array (MMA). The proposed MMA architecture uses time-multiplexed processing, so that the efficiency of hardware utilization is greatly enhanced. Furthermore, the processing flow utilizes parallel processing, such that the centering, the calculation of the covariance matrix, and the EVD are conducted simultaneously and are individually pipelined to maximize throughput. This article presents the architecture, circuit design, and performance estimates based on post-layout extraction of the proposed preprocessing ICA accelerator. The proposed design achieves a throughput of 40.7 kMatrices/s at a complexity of 73.3 kGE.
Lu, H.-H., Shen, C.-A., Fouda, M. E., & Eltawil, A. M. (2022). Configurable Independent Component Analysis Preprocessing Accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1–13. https://doi.org/10.1109/tvlsi.2022.3209538
The work of Hsi-Hung Lu and Chung-An Shen was supported by the Ministry of Science and Technology, Taiwan, under Grant MOST 110-2221-E-011-155 and Grant MOST 111-2221-E-011-136- MY3. The work of Ahmed M. Eltawil was supported by the King Abdullah University of Science and Technology.