High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-kappa/Metal Gate

Abstract
We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies. SiNWs are fabricated by deep Si reactive ion etching, gate-stack is formed by atomic layer deposition, and metal salicide is utilized as drain contact. The fabricated p-type gate-all-around SiNW metal-oxide-semiconductor field-effect transistors that have a gate length of 320 nm exhibit excellent characteristics with ION/IOFF > 104, subthreshold slope of 87 mV/decade, and 25 mV/V of drain-induced barrier lowering. Low-temperature characteristics are also presented. The demonstrated devices have potential applications in novel low-power logic circuits and as selection transistors for 4F2 cross-point memory cells.

Citation
Yujia Zhai, Mathew, L., Rao, R., Palard, M., Chopra, S., Ekerdt, J. G., … Banerjee, S. K. (2014). High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High- $\kappa $ /Metal Gate. IEEE Transactions on Electron Devices, 61(11), 3896–3900. doi:10.1109/ted.2014.2353658

Acknowledgements
This work was supported in part by the King Abdullah University of Science and Technology, Thuwal, Saudi Arabia, in part by the National Science Foundation, Nanosystems Engineering Research Center, through the Nanomanufacturing Systems for Mobile Computing and Mobile Energy Technologies, and in part by the National Nanotechnology Infrastructure Network Programs. The review of this brief was arranged by Editor W. Tsai.

Publisher
Institute of Electrical and Electronics Engineers (IEEE)

Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES

DOI
10.1109/TED.2014.2353658

Additional Links
http://ieeexplore.ieee.org/document/6902756/

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