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dc.contributor.authorSmagulova, Kamilya
dc.contributor.authorFouda, Mohammed E.
dc.contributor.authorKurdahi, Fadi
dc.contributor.authorSalama, Khaled N.
dc.contributor.authorEltawil, Ahmed
dc.date.accessioned2021-09-14T12:46:56Z
dc.date.available2021-09-14T12:46:56Z
dc.date.issued2021-09-08
dc.identifier.urihttp://hdl.handle.net/10754/671210
dc.description.abstractDeep Neural Networks (DNNs), as a subset of Machine Learning (ML) techniques, entail that real-world data can be learned and that decisions can be made in real-time. However, their wide adoption is hindered by a number of software and hardware limitations. The existing general-purpose hardware platforms used to accelerate DNNs are facing new challenges associated with the growing amount of data and are exponentially increasing the complexity of computations. An emerging non-volatile memory (NVM) devices and processing-in-memory (PIM) paradigm is creating a new hardware architecture generation with increased computing and storage capabilities. In particular, the shift towards ReRAM-based in-memory computing has great potential in the implementation of area and power efficient inference and in training large-scale neural network architectures. These can accelerate the process of the IoT-enabled AI technologies entering our daily life. In this survey, we review the state-of-the-art ReRAM-based DNN many-core accelerators, and their superiority compared to CMOS counterparts was shown. The review covers different aspects of hardware and software realization of DNN accelerators, their present limitations, and future prospectives. In particular, comparison of the accelerators shows the need for the introduction of new performance metrics and benchmarking standards. In addition, the major concerns regarding the efficient design of accelerators include a lack of accuracy in simulation tools for software and hardware co-design.
dc.publisherarXiv
dc.relation.urlhttps://arxiv.org/pdf/2109.03934.pdf
dc.rightsArchived with thanks to arXiv
dc.titleResistive Neural Hardware Accelerators
dc.typePreprint
dc.contributor.departmentComputer, Electrical and Mathematical Science and Engineering (CEMSE) Division
dc.contributor.departmentElectrical and Computer Engineering Program
dc.contributor.departmentSensors Lab
dc.eprint.versionPre-print
dc.contributor.institutionElectrical Engineering and Computer Science Dept., University of California–Irvine, Irvine, CA 92697 USA.
dc.identifier.arxivid2109.03934
kaust.personSmagulova, Kamilya
kaust.personSalama, Khaled N.
kaust.personEltawil, Ahmed Mohamed
refterms.dateFOA2021-09-14T12:50:15Z


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