KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Permanent link to this recordhttp://hdl.handle.net/10754/668980
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AbstractFor more than four decades, Moore’s law has been driving the semiconductor industry where the number of transistors per chip roughly doubles every 18–24 months at a constant cost. Transistors have been relentlessly evolving from the first Ge transistor invented at Bell Labs in 1947 to planar Si metal-oxide semiconductor field-effect transistor (MOSFET), then to strained SiGe source/drain (S/D) in the 90- and 65-nm technology nodes and high-κ/metal gate stack introduced at the 45- and 32-nm nodes, then to the current 3D transistors (Fin field-effect transistors (FinFETs)) introduced at the 22-nm node in 2011 (Figure 1.1). In extremely scaled transistors, the parasitic and contact resistances greatly deteriorate the drive current and degrade the circuit speed. Thus, miniaturization of devices so far has been possible due to changes in dielectric, S/D, and contacts materials/processes, and innovations in lithography processes, in addition to changes in the device architecture [1, 2].
CitationEl-Atab, N., & Hussain, M. M. (2018). The Future of CMOS: More Moore or a New Disruptive Technology? Advanced Nanoelectronics, 1–31. doi:10.1002/9783527811861.ch1
PublisherWiley-VCH Verlag GmbH & Co. KGaA