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dc.contributor.authorGuo, Wenzhe
dc.contributor.authorYantir, Hasan Erdem
dc.contributor.authorFouda, Mohamed E.
dc.contributor.authorEltawil, Ahmed
dc.contributor.authorSalama, Khaled N.
dc.date.accessioned2021-02-14T12:28:34Z
dc.date.available2021-02-14T12:28:34Z
dc.date.issued2021
dc.date.submitted2020-02-18
dc.identifier.citationGuo, W., Yantir, H. E., Fouda, M. E., Eltawil, A. M., & Salama, K. N. (2021). Toward the Optimal Design and FPGA Implementation of Spiking Neural Networks. IEEE Transactions on Neural Networks and Learning Systems, 1–15. doi:10.1109/tnnls.2021.3055421
dc.identifier.issn2162-2388
dc.identifier.doi10.1109/TNNLS.2021.3055421
dc.identifier.urihttp://hdl.handle.net/10754/667399
dc.description.abstractThe performance of a biologically plausible spiking neural network (SNN) largely depends on the model parameters and neural dynamics. This article proposes a parameter optimization scheme for improving the performance of a biologically plausible SNN and a parallel on-field-programmable gate array (FPGA) online learning neuromorphic platform for the digital implementation based on two numerical methods, namely, the Euler and third-order Runge-Kutta (RK3) methods. The optimization scheme explores the impact of biological time constants on information transmission in the SNN and improves the convergence rate of the SNN on digit recognition with a suitable choice of the time constants. The parallel digital implementation leads to a significant speedup over software simulation on a general-purpose CPU. The parallel implementation with the Euler method enables around 180x (20x) training (inference) speedup over a Pytorch-based SNN simulation on CPU. Moreover, compared with previous work, our parallel implementation shows more than 300x (240x) improvement on speed and 180x (250x) reduction in energy consumption for training (inference). In addition, due to the high-order accuracy, the RK3 method is demonstrated to gain 2x training speedup over the Euler method, which makes it suitable for online training in real-time applications.
dc.description.sponsorshipThis work was supported by the King Abdullah University of Science and Technology (KAUST) AI Initiative, Saudi Arabia
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.relation.urlhttps://ieeexplore.ieee.org/document/9353400/
dc.relation.urlhttps://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9353400
dc.rights(c) 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
dc.subjectEuler method
dc.subjectfield-programmable gate array (FPGA) platform
dc.subjectneuromorphic computing
dc.subjecton-chip learning
dc.subjectparallel architecture
dc.subjectparameter optimization
dc.subjectRunge-Kutta (RK) method
dc.subjectspiking neural network (SNN)
dc.subjectunsupervised spike-timing-dependent plasticity (STDP) learning.
dc.titleToward the Optimal Design and FPGA Implementation of Spiking Neural Networks
dc.typeArticle
dc.contributor.departmentElectrical Engineering Program
dc.contributor.departmentElectrical Engineering
dc.contributor.departmentPhysical Science and Engineering (PSE) Division
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
dc.identifier.journalIEEE Transactions on Neural Networks and Learning Systems
dc.eprint.versionPost-print
dc.contributor.institutionDepartment of EECS, University of California-Irvine, Irvine, CA 92612 USA.
dc.identifier.pages1-15
kaust.personGuo, Wenzhe
kaust.personYantir, Hasan Erdem
kaust.personEltawil, Ahmed Mohamed
kaust.personSalama, Khaled N.
dc.date.accepted2021-01-25
refterms.dateFOA2021-02-14T13:09:33Z


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