On-Chip Error-triggered Learning of Multi-layer Memristive Spiking Neural Networks
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ArticleDate
2020Permanent link to this record
http://hdl.handle.net/10754/666121
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Recent breakthroughs in neuromorphic computing show that local forms of gradient descent learning are compatible with Spiking Neural Networks (SNNs) and synaptic plasticity. Although SNNs can be scalably implemented using neuromorphic VLSI, an architecture that can learn using gradient-descent in situ is still missing. In this paper, we propose a local, gradient-based, error-triggered learning algorithm with online ternary weight updates. The proposed algorithm enables online training of multi-layer SNNs with memristive neuromorphic hardware showing a small loss in the performance compared with the state-of-the-art. We also propose a hardware architecture based on memristive crossbar arrays to perform the required vector-matrix multiplications. The necessary peripheral circuitry including presynaptic, post-synaptic and write circuits required for online training, have been designed in the subthreshold regime for power saving with a standard 180nm CMOS process.Citation
Payvand, M., Fouda, M. E., Kurdahi, F., Eltawil, A. M., & Neftci, E. O. (2020). On-Chip Error-triggered Learning of Multi-layer Memristive Spiking Neural Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 1–1. doi:10.1109/jetcas.2020.3040248Publisher
IEEEarXiv
2011.10852Additional Links
https://ieeexplore.ieee.org/document/9268117/https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9268117
http://arxiv.org/pdf/2011.10852
ae974a485f413a2113503eed53cd6c53
10.1109/JETCAS.2020.3040248