Giant Electroresistance Switching of Two-dimensional Ferroelectric α-In2Se3on p+-Si
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Accepted manuscript
Type
Conference PaperAuthors
Lee, Ko ChunRetamal, Jose Ramon Duran
Xue, Fei
Cheng, Bin
Tang, Hao Ling
Chiu, Ming Hui
Hu, Wei Jin
Wu, Chih I.
Chen, Mei Hsin
Li, Lain-Jong

Lien, Chen Hsin
He, Jr-Hau

KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) DivisionElectrical Engineering Program
KAUST Solar Center (KSC)
King Abdullah University of Science and Technology,Computer, Electrical and Mathematical Science and Engineering Division,Thuwal,Kingdom of Saudi Arabia
Material Science and Engineering Program
Nano Energy Lab
Physical Science and Engineering (PSE) Division
Date
2020-09-23Online Publication Date
2020-09-23Print Publication Date
2020-08Permanent link to this record
http://hdl.handle.net/10754/665813
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Recently, the demonstration of the ferroelectricity of phase In2Se3( -In2Se3) has opened new opportunities to develop two-dimensional small bandgap ferroelectric memories. Conventional ferroelectric hetero-junction memories have been widely studied but the performance is still limited by the large bandgap of oxide-based ferroelectric materials and limits the diode ON current and results in low ON/OFF ratio. Accordingly, we propose a novel resistive switching memory device based on the unique ferroelectric and semiconductor properties of -In2Se3. By forming the hetero-junction of -In2Se3 with the highly degenerated \mathrmp+ -Si substrate, we achieve a giant ferroelectric resistive ON/OFF ratio of 2.3 106.Citation
Lee, K.-C., Retamal, J. R. D., Xue, F., Cheng, B., Tang, H.-L., Chiu, M.-H., … He, J.-H. (2020). Giant Electroresistance Switching of Two-dimensional Ferroelectric α-In2Se3 on p+-Si. 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA). doi:10.1109/vlsi-tsa48913.2020.9203707Conference/Event name
2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020ISBN
9781728142326Additional Links
https://ieeexplore.ieee.org/document/9203707/ae974a485f413a2113503eed53cd6c53
10.1109/VLSI-TSA48913.2020.9203707