Type
ArticleAuthors
Shahid, HamzaAlzaher, Hussain
KAUST Grant Number
KAUST-KFUPM Initiative (KKI) program project #1Date
2019-05-25Online Publication Date
2019-05-25Print Publication Date
2020-03Permanent link to this record
http://hdl.handle.net/10754/656312
Metadata
Show full item recordAbstract
A low-voltage and ultra-low power sub-Hertz timer using transistor operating in sub-threshold region is proposed. The sub-Hertz operation is achieved by controlling the amount of currents charging and discharging the timer’s capacitor instead of using large passive components. Pulse width modulation is accomplished by sizing the transistors in charging and discharging control blocks. The timer is working from a single supply voltage of as low as 0.4 V. The circuit is designed in a standard CMOS 150 nm and simulated using Cadence. Simulation results show an oscillation frequency of as low as 0.0217 Hz (a period of 46 s) while using integrable capacitor (100 pF). Its average power consumption for one period is 13.91 pW.Citation
Shahid, H., & Alzaher, H. (2019). A New pW CMOS Sub-Hertz Timer. Arabian Journal for Science and Engineering. doi:10.1007/s13369-019-03928-1Sponsors
The authors would like to thank the support of KAUST-KFUPM Initiative (KKI) program project #1.Publisher
Springer NatureAdditional Links
http://link.springer.com/10.1007/s13369-019-03928-1ae974a485f413a2113503eed53cd6c53
10.1007/s13369-019-03928-1