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dc.contributor.authorKang, Soo Cheol
dc.contributor.authorKim, Seung Mo
dc.contributor.authorJung, Ukjin
dc.contributor.authorKim, Yonghun
dc.contributor.authorPark, Woojin
dc.contributor.authorLee, Byoung Hun
dc.date.accessioned2019-08-01T12:26:55Z
dc.date.available2019-08-01T12:26:55Z
dc.date.issued2019-05-10
dc.identifier.citationKang, S. C., Kim, S. M., Jung, U., Kim, Y., Park, W., & Lee, B. H. (2019). Interface state degradation during AC positive bias temperature instability stress. Solid-State Electronics, 158, 46–50. doi:10.1016/j.sse.2019.05.006
dc.identifier.doi10.1016/j.sse.2019.05.006
dc.identifier.urihttp://hdl.handle.net/10754/656298
dc.description.abstractThe reliability of a bulk fin field-effect transistor (FinFET) with a high-k dielectric/metal-gate stack has been investigated by comparing the effects of DC and AC stresses. It is well known that the relaxation during the off-cycle of the AC stress decreases the Vth shift and enhances the device lifetime due to electron detrapping from the high-k dielectric. We found that the relaxation in the interface traps is significantly weaker than that of bulk traps during the unipolar and bipolar AC stresses. The weak recovery is attributed to the concurrent interface state generation during a positive-bias temperature instability (PBTI) stress. Eventually, the interface traps became a major source of the device drift (over 60%) at the high temperature of 400 K. This finding suggests that a new strategy is required to address the PBTI reliability focusing on the residual interface states as well as the bulk trapping, particularly at a high temperature.
dc.description.sponsorshipThis study was partly supported by the Nano Materials Technology Development Program (2016M3A7B4909941) and Creative Materials Discovery Program on Creative Multilevel Research Center (2015M3D1A1068062) through the National Research Foundation (NRF) of Korea, funded by the Ministry of Science and ICT, and by SAMSUNG System LSI.
dc.publisherElsevier BV
dc.relation.urlhttps://linkinghub.elsevier.com/retrieve/pii/S003811011830604X
dc.rightsNOTICE: this is the author’s version of a work that was accepted for publication in Solid-State Electronics. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Solid-State Electronics, [[Volume], [Issue], (2019-08-01)] DOI: 10.1016/j.sse.2019.05.006 . © 2019. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.subjectBias temperature instability
dc.subjectBipolar AC stress
dc.subjectFin field-effect transistor
dc.subjectHigh-k/metal gate
dc.subjectInterface degradation
dc.subjectRecovery
dc.titleInterface state degradation during AC positive bias temperature instability stress
dc.typeArticle
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
dc.identifier.journalSolid-State Electronics
dc.rights.embargodate2021-08-01
dc.eprint.versionPost-print
dc.contributor.institutionCenter for Emerging Electronic Devices and Systems (CEEDS), School of Material Science and Engineering, Gwangju Institute of Science and Technology (GIST), Gwangju 61005, South Korea
dc.contributor.institutionSystem LSI Division, SAMSUNG Semiconductor, Giheung, South Korea
dc.contributor.institutionDepartment of Advanced Functional Thin Films, Surface Technology Division, Korea Institute of Materials Science, 797 Changwondaero, Seongsan-Gu, Gyeongnam, South Korea
kaust.personPark, Woojin
dc.date.published-online2019-05-10
dc.date.published-print2019-08


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NOTICE: this is the author’s version of a work that was accepted for publication in Solid-State Electronics. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Solid-State Electronics, [[Volume], [Issue], (2019-08-01)] DOI: 10.1016/j.sse.2019.05.006 . © 2019. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/
Except where otherwise noted, this item's license is described as NOTICE: this is the author’s version of a work that was accepted for publication in Solid-State Electronics. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Solid-State Electronics, [[Volume], [Issue], (2019-08-01)] DOI: 10.1016/j.sse.2019.05.006 . © 2019. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/