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dc.contributor.authorSoliman, Shady
dc.contributor.authorJaela, Mohammed A.
dc.contributor.authorAbotaleb, Abdelrhman M.
dc.contributor.authorHassan, Youssef
dc.contributor.authorAbdelghany, Mohamed A.
dc.contributor.authorAbdel-Hamid, Amr T.
dc.contributor.authorSalama, Khaled N.
dc.contributor.authorMostafa, Hassan
dc.date.accessioned2019-07-30T12:26:06Z
dc.date.available2019-07-30T12:26:06Z
dc.date.issued2019-06-26
dc.identifier.citationSoliman, S., Jaela, M. A., Abotaleb, A. M., Hassan, Y., Abdelghany, M. A., Abdel-Hamid, A. T., … Mostafa, H. (2019). FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping. Integration, 68, 108–121. doi:10.1016/j.vlsi.2019.06.004
dc.identifier.doi10.1016/j.vlsi.2019.06.004
dc.identifier.urihttp://hdl.handle.net/10754/656239
dc.description.abstractInternet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1).
dc.description.sponsorshipThis work was supported by the Egyptian Information Technology Industry Development Agency (ITIDA) under ITAC Program PRP2018.R25.23.
dc.publisherElsevier BV
dc.relation.urlhttps://linkinghub.elsevier.com/retrieve/pii/S0167926019300537
dc.rightsNOTICE: this is the author’s version of a work that was accepted for publication in Integration. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Integration, [[Volume], [Issue], (2019-06-26)] DOI: 10.1016/j.vlsi.2019.06.004 . © 2019. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/
dc.subjectCAESAR
dc.subjectFPGA
dc.subjectDPR
dc.subjectCryptography
dc.subjectHopping
dc.subjectAEAD
dc.subjectIoT
dc.titleFPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
dc.typeArticle
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
dc.contributor.departmentElectrical Engineering
dc.contributor.departmentElectrical Engineering Program
dc.identifier.journalIntegration
dc.rights.embargodate2021-06-26
dc.eprint.versionPost-print
dc.contributor.institutionElectronics Department, German University in Cairo, Cairo 11835, Egypt
dc.contributor.institutionElectronics and Communications Engineering Department, Cairo University, Giza 12613, Egypt
dc.contributor.institutionIntegrated Electronic Systems Lab, GTU Darmstadt, Germany
dc.contributor.institutionUniversity of Science and Technology, Nanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, October Gardens, 6th of October, Giza 12578, Egypt
kaust.personSalama, Khaled N.
dc.date.published-online2019-06-26
dc.date.published-print2019-09


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