FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
Jaela, Mohammed A.
Abotaleb, Abdelrhman M.
Abdelghany, Mohamed A.
Abdel-Hamid, Amr T.
Salama, Khaled N.
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Online Publication Date2019-06-26
Print Publication Date2019-09
Embargo End Date2021-06-26
Permanent link to this recordhttp://hdl.handle.net/10754/656239
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AbstractInternet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1).
CitationSoliman, S., Jaela, M. A., Abotaleb, A. M., Hassan, Y., Abdelghany, M. A., Abdel-Hamid, A. T., … Mostafa, H. (2019). FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping. Integration, 68, 108–121. doi:10.1016/j.vlsi.2019.06.004
SponsorsThis work was supported by the Egyptian Information Technology Industry Development Agency (ITIDA) under ITAC Program PRP2018.R25.23.