AdvisorsDe Wolf, Stefaan
KAUST DepartmentPhysical Sciences and Engineering (PSE) Division
Permanent link to this recordhttp://hdl.handle.net/10754/652926
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AbstractSilicon photovoltaic (PV) is a promising solution for energy shortage and environmental pollution. We are experiencing an era when PV is exponentially increasing. Global cumulative installation had reached 380 GW in 2017. Among which, silicon-based PV productions share more than 90% market. Performance of the first two-generation commercial popular silicon solar cells - Al-BSF and PERC - are limited by metal/Si contacts, where interface defects significantly reduce the open-circuit voltage. In this context, full-area passivation concepts are proposed for c-Si solar cells, with expectation to enhance the efficiency via reducing carrier recombination loss at the contact regions. In this thesis, poly silicon on oxide (POLO) passivating contact is developed for high efficiency c-Si solar cells. We unveiled the working mechanisms of POLO cells and then optimized the device performance based on our conclusion. We use boiling nitric acid to oxidize c-Si surface, which is of significance to determine the POLO working mechanisms. Phosphorus and boron doped silicon films are deposited by plasma enhanced vapor deposition (PECVD) or low-pressure vapor deposition (LPCVD) followed by high temperature (>800°C) annealing. SiOx structural evolution process under different annealing temperature was observed and the corresponding effects on passivation have been elucidated. The carrier transport mechanisms in the POLO contact annealed at high temperature, e.g. 800°C 900°C, were explored. We unveil that carrier transport in POLO structure is a combination of tunneling and pinhole transport, but dominant at varied temperature regions. Phosphorus-doped n-type POLO contact is optimized by several parameters, such as doping concentration, film thickness, annealing temperature, film deposition temperature, film relaxation time during annealing process, etc. We successfully obtained minority carrier lifetime over 10ms and contact resistivity lower than 30 mΩ·cm2. Boron-doped p-type POLO contact is also optimized by changing the doping concentration and annealing temperature. Finally, further hydrogen passivation is applied to enhance p-type POLO contact passivation, achieving an iVoc>690 mV, J0 <5 fA/cm2 and contact resistivity 1.3 mΩ·cm2. With the optimized n-type and p-type POLO contacts, an efficiency over 18% is achieved on n-type c-Si solar cells with a flat front surface.
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Colloidal Photoluminescent Amorphous Porous Silicon, Methods Of Making Colloidal Photoluminescent Amorphous Porous Silicon, And Methods Of Using Colloidal Photoluminescent Amorphous Porous SiliconChaieb, Saharoui; Mughal, Asad Jahangir (2015-04-09) [Patent]Embodiments of the present disclosure provide for a colloidal photoluminescent amorphous porous silicon particle suspension, methods of making a colloidal photoluminescent amorphous porous silicon particle suspension, methods of using a colloidal photoluminescent amorphous porous silicon particle suspension, and the like.
Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)Hussain, Muhammad Mustafa; Rojas, Jhonathan Prieto; Sevilla, Galo T. (Micro- and Nanotechnology Sensors, Systems, and Applications V, SPIE-Intl Soc Optical Eng, 2013-05-30) [Conference Paper]Today’s information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor – heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon – industry’s darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%). © (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Design criteria for XeF2 enabled deterministic transformation of bulk silicon (100) into flexible silicon layerHussain, Aftab M.; Shaikh, Sohail F.; Hussain, Muhammad Mustafa (AIP Advances, AIP Publishing, 2016-07-15) [Article]Isotropic etching of bulk silicon (100) using Xenon Difluoride (XeF2) gas presents a unique opportunity to undercut and release ultra-thin flexible silicon layers with pre-fabricated state-of-the-art Complementary Metal Oxide Semiconductor (CMOS) electronics. In this work, we present design criteria and mechanism with a comprehensive mathematical model for this method. We consider various trench geometries and parametrize important metrics such as etch time, number of cycles and area efficiency in terms of the trench diameter and spacing so that optimization can be done for specific applications. From our theoretical analysis, we conclude that a honeycomb-inspired hexagonal distribution of trenches can produce the most efficient release of ultra-thin flexible silicon layers in terms of the number of etch cycles, while a rectangular distribution of circular trenches provides the most area efficient design. The theoretical results are verified by fabricating and releasing (varying sizes) flexible silicon layers. We observe uniform translation of design criteria into practice for etch distances and number of etch cycles, using reaction efficiency as a fitting parameter.