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dc.contributor.authorLi, Ren
dc.contributor.authorAlhadrami, Reem
dc.contributor.authorFariborzi, Hossein
dc.date.accessioned2019-03-10T10:35:08Z
dc.date.available2019-03-10T10:35:08Z
dc.date.issued2019-05
dc.identifier.citationLi, R., Alhadrami, R., & Fariborzi, H. (2019). BEOL NEM Relay Based Sequential Logic Circuits. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/iscas.2019.8702123
dc.identifier.doi10.1109/ISCAS.2019.8702123
dc.identifier.urihttp://hdl.handle.net/10754/631395
dc.description.abstractIn recent years Nano-electromechanical (NEM) relays have been proposed as promising candidates to complement or replace CMOS technology in ultra-low power applications, due to their zero off-state leakage and abrupt turn on/off behavior. The development of the air gap technology enables the implementation of vertical relays, compatible with the Back-End-of-Line (BEOL) CMOS fabrication processes. In this work, we present the design, implementation, and analysis of integrated sequential logic blocks built with BEOL NEM relays, using custom and commercial modeling and simulation tools. While relay circuits are inevitably slower than transistor counterparts due to the mechanical nature of the operation, we show that the proposed circuits offer more than one order of magnitude saving on energy and area consumption. This is particularly attractive in the Internet of Things (IoT) applications, where the requirements for ultra-low power consumption are significantly stricter than those for computation speed.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.relation.urlhttps://ieeexplore.ieee.org/document/8702123/
dc.relation.urlhttps://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8702123
dc.rightsArchived with thanks to (c) 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
dc.subjectBEOL NEM relay
dc.subjectSequential logic circuits
dc.subjectUltra-low power VLSI design
dc.titleBEOL NEM Relay Based Sequential Logic Circuits
dc.typeConference Paper
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
dc.contributor.departmentElectrical Engineering
dc.contributor.departmentElectrical Engineering Program
dc.conference.date26-29 May 2019
dc.conference.name2019 IEEE International Symposium on Circuits and Systems (ISCAS)
dc.conference.locationSapporo, Japan
dc.eprint.versionPost-print
dc.contributor.institutionElectrical and Computer Engineering Department, Effat University, Jeddah, Saudi Arabia
pubs.publication-statusAccepted
kaust.personLi, Ren
kaust.personFariborzi, Hossein
refterms.dateFOA2019-03-10T10:35:09Z


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