StrongARM Latch Comparator Performance Enhancement by Implementing Clocked Forward Body Biasing
Name:
FBB for comparatr V27 (Final submitted version).pdf
Size:
717.7Kb
Format:
PDF
Description:
Accepted Manuscript
Type
Conference PaperAuthors
Alshehri, AbdullahAl-Qadasi, Mohammed
Almansouri, Abdullah Saud Mohammed
Al Attar, Talal
Fariborzi, Hossein

KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) DivisionElectrical Engineering Program
Date
2019-01-24Online Publication Date
2019-01-24Print Publication Date
2018-12Permanent link to this record
http://hdl.handle.net/10754/631288
Metadata
Show full item recordAbstract
In this paper, we propose a forward body biasing technique to enhance the performance of the StrongARM comparators. We apply this technique, which is mainly based on clocked tuning of the threshold voltage of the NMOS cross-coupled transistors, to different architectures, namely: Kobayashi, Razavi, and Improved StrongARM comparators. The circuits are simulated in the standard 65nm CMOS technology and performance improvement of up to 20.8% has been achieved while maintaining the same energy loss.Citation
Alshehri A, Al-Qadasi M, Almansouri AS, Al-Attar T, Fariborzi H (2018) StrongARM Latch Comparator Performance Enhancement by Implementing Clocked Forward Body Biasing. 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS). Available: http://dx.doi.org/10.1109/icecs.2018.8617903.Conference/Event name
2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)Additional Links
https://ieeexplore.ieee.org/document/8617903ae974a485f413a2113503eed53cd6c53
10.1109/icecs.2018.8617903