A High Speed Dynamic StrongARM Latch Comparator

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Type
Conference Paper
Authors
Al-Qadasi, Mohammed
Alshehri, Abdullah
Almansouri, Abdullah Saud Mohammed
Al Attar, Talal
Fariborzi, Hossein cc
KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Date
2019-02-28
Online Publication Date
2019-02-28
Print Publication Date
2018-08
Permanent link to this record
http://hdl.handle.net/10754/631285

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Abstract
In this paper, a new design has been proposed for a high speed, low power StrongARM latch in 65nm CMOS technology. Latching speed improvements of 18% and 16% have been achieved in comparison to the conventional [4] and improved StrongARM [5], respectively, while the energy consumption has also been reduced.
Citation
Al-Qadasi M, Alshehri A, Almansouri AS, Al-Attar T, Fariborzi H (2018) A High Speed Dynamic StrongARM Latch Comparator. 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). Available: http://dx.doi.org/10.1109/mwscas.2018.8624100.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Journal
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
Conference/Event name
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
DOI
10.1109/mwscas.2018.8624100
Additional Links
https://ieeexplore.ieee.org/document/8624100
Collections
Conference Papers; Electrical and Computer Engineering Program; Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division