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A High Speed Dynamic StrongARM Comparator - Paper.pdf
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Accepted Manuscript
Type
Conference PaperAuthors
Al-Qadasi, MohammedAlshehri, Abdullah
Almansouri, Abdullah Saud Mohammed
Al Attar, Talal
Fariborzi, Hossein

KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) DivisionElectrical Engineering Program
Date
2019-02-28Online Publication Date
2019-02-28Print Publication Date
2018-08Permanent link to this record
http://hdl.handle.net/10754/631285
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Show full item recordAbstract
In this paper, a new design has been proposed for a high speed, low power StrongARM latch in 65nm CMOS technology. Latching speed improvements of 18% and 16% have been achieved in comparison to the conventional [4] and improved StrongARM [5], respectively, while the energy consumption has also been reduced.Citation
Al-Qadasi M, Alshehri A, Almansouri AS, Al-Attar T, Fariborzi H (2018) A High Speed Dynamic StrongARM Latch Comparator. 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). Available: http://dx.doi.org/10.1109/mwscas.2018.8624100.Conference/Event name
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)Additional Links
https://ieeexplore.ieee.org/document/8624100ae974a485f413a2113503eed53cd6c53
10.1109/mwscas.2018.8624100