Almansouri, Abdullah Saud Mohammed
Al Attar, Talal
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Online Publication Date2019-02-28
Print Publication Date2018-08
Permanent link to this recordhttp://hdl.handle.net/10754/631285
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AbstractIn this paper, a new design has been proposed for a high speed, low power StrongARM latch in 65nm CMOS technology. Latching speed improvements of 18% and 16% have been achieved in comparison to the conventional  and improved StrongARM , respectively, while the energy consumption has also been reduced.
CitationAl-Qadasi M, Alshehri A, Almansouri AS, Al-Attar T, Fariborzi H (2018) A High Speed Dynamic StrongARM Latch Comparator. 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). Available: http://dx.doi.org/10.1109/mwscas.2018.8624100.
Conference/Event name2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)