A New Design Methodology for Time-Based Capacitance-to-Digital Converters (T-CDCs)
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Online Publication Date2018-09-27
Print Publication Date2018-11
Permanent link to this recordhttp://hdl.handle.net/10754/630620
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AbstractThis paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts a new design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, the input sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter (CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter (TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13 μm CMOS technology. This T-CDC consumes 8.42 μW and achieves a maximum SNR of 45.14 dB with a conversion time of 1 μs that corresponds to a figure of merit (FoM) of 16.4 fJ/Conv.
CitationHassan AH, Fouad A, Mostafa H, Salama KN, Soliman AM (2018) A New Design Methodology for Time-Based Capacitance-to-Digital Converters (T-CDCs). AEU - International Journal of Electronics and Communications 96: 238–245. Available: http://dx.doi.org/10.1016/j.aeue.2018.09.034.
SponsorsA preliminary version of this work is published in ICM 2017 conference . This research was partially funded by ONE Lab at Cairo University,Zewail City of Science and Technology, and King Abdullah University of Science and Technology (KAUST).