AuthorsAlmansouri, Abdullah Saud Mohammed
Salama, Khaled N.
Al Attar, Talal
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Online Publication Date2018-08-17
Print Publication Date2018-07
Permanent link to this recordhttp://hdl.handle.net/10754/630561
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AbstractThis work proposes an efficient 4-bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1-out-of-15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1-out-of-n code. The proposed 4-bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes 292 μ W at 1.6 GHz sampling frequency, has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step.
CitationAlmansouri AS, Alturki A, Fariborzi H, Salama KN, Al-Attar T (2018) A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture. 2018 14th Conference on PhD Research in Microelectronics and Electronics (PRIME). Available: http://dx.doi.org/10.1109/PRIME.2018.8430349.
Conference/Event name14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018