Design and analysis of 2T-2M Ternary content addressable memories
Type
Conference PaperAuthors
Bahloul, MohamedFouda, M. E.
Naous, Rawan

Zidan, Mohammed A.

Eltawil, A. M.
Kurdahi, F.
Salama, Khaled N.

KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) DivisionElectrical Engineering Program
Physical Science and Engineering (PSE) Division
Sensors Lab
Date
2017-10-24Online Publication Date
2017-10-24Print Publication Date
2017-08Permanent link to this record
http://hdl.handle.net/10754/626785
Metadata
Show full item recordAbstract
Associate and approximate computing using resistive memory based Ternary Content Addressable Memory is becoming widely used. In this paper, a simplified model based analysis of a 2T2M-Ternary Content Addressable Memory using memristors is introduced. A comprehensive study is presented taking into consideration different circuit parameters and parasitic effects. Parameters such as the memristor Rh/Rl ratio, transistor technology, operating frequency, and memory width are taken into consideration. The proposed model is verified with SPICE showing a high degree of matching between theory and simulation. The utility of the model is established using a design example.Citation
Bahloul MA, Fouda ME, Naous R, Zidan MA, Eltawil AM, et al. (2017) Design and analysis of 2T-2M Ternary content addressable memories. 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). Available: http://dx.doi.org/10.1109/mwscas.2017.8053201.Conference/Event name
60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017Additional Links
http://ieeexplore.ieee.org/document/8053201/ae974a485f413a2113503eed53cd6c53
10.1109/mwscas.2017.8053201