Design and analysis of 2T-2M Ternary content addressable memories

Type
Conference Paper
Authors
Bahloul, M. A.
Fouda, M. E.
Naous, Rawan cc
Zidan, Mohammed A. cc
Eltawil, A. M.
Kurdahi, F.
Salama, Khaled N. cc
KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Physical Sciences and Engineering (PSE) Division
Date
2017-10-24

Metadata
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Abstract
Associate and approximate computing using resistive memory based Ternary Content Addressable Memory is becoming widely used. In this paper, a simplified model based analysis of a 2T2M-Ternary Content Addressable Memory using memristors is introduced. A comprehensive study is presented taking into consideration different circuit parameters and parasitic effects. Parameters such as the memristor Rh/Rl ratio, transistor technology, operating frequency, and memory width are taken into consideration. The proposed model is verified with SPICE showing a high degree of matching between theory and simulation. The utility of the model is established using a design example.
Citation
Bahloul MA, Fouda ME, Naous R, Zidan MA, Eltawil AM, et al. (2017) Design and analysis of 2T-2M Ternary content addressable memories. 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). Available: http://dx.doi.org/10.1109/mwscas.2017.8053201.
Publisher
IEEE
Journal
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
Conference/Event name
60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
DOI
10.1109/mwscas.2017.8053201
Handle URI
http://hdl.handle.net/10754/626785
Additional Links
http://ieeexplore.ieee.org/document/8053201/
Collections
Conference Papers; Physical Sciences and Engineering (PSE) Division; Electrical Engineering Program; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division