Improved StrongARM latch comparator: Design, analysis and performance evaluation

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Type
Conference Paper
Authors
Almansouri, Abdullah Saud Mohammed
Al-Turki, Abdullah Turki
Alshehri, Abdullah
Al Attar, Talal
Al Attar, Talal
Fariborzi, Hossein cc
KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Date
2017-07-13
Online Publication Date
2017-07-13
Print Publication Date
2017-06
Permanent link to this record
http://hdl.handle.net/10754/625683

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Abstract
This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.
Citation
Almansouri A, Alturki A, Alshehri A, Al-Attar T, Fariborzi H (2017) Improved StrongARM latch comparator: Design, analysis and performance evaluation. 2017 13th Conference on PhD Research in Microelectronics and Electronics (PRIME). Available: http://dx.doi.org/10.1109/PRIME.2017.7974114.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Journal
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Conference/Event name
13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017
DOI
10.1109/PRIME.2017.7974114
Additional Links
http://ieeexplore.ieee.org/document/7974114/
Collections
Conference Papers; Electrical and Computer Engineering Program; Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division