Transparent Flash Memory using Single Ta2O5 Layer for both Charge Trapping and Tunneling Dielectrics
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Online Publication Date2017-06-22
Print Publication Date2017-07-05
Permanent link to this recordhttp://hdl.handle.net/10754/624989
MetadataShow full item record
AbstractWe report reproducible multibit transparent flash memory in which a single solution-derived Ta2O5 layer is used simultaneously as charge trapping and tunneling layer. This is different from conventional flash cells, where two different dielectric layers are typically used. Under optimized programming/erasing operations, the memory device shows excellent programmable memory characteristics with a maximum memory window of ~10 V. Moreover, the flash memory device shows a stable 2-bit memory performance, good reliability, including data retention for more than 104 sec and endurance performance for more than 100 cycles. The use of a common charge trapping and tunneling layer can simplify advanced flash memory fabrication.
CitationHota MK, Alshammari FH, Salama KN, Alshareef HN (2017) Transparent Flash Memory using Single Ta2O5 Layer for both Charge Trapping and Tunneling Dielectrics. ACS Applied Materials & Interfaces. Available: http://dx.doi.org/10.1021/acsami.7b03078.
SponsorsResearch reported in this publication was supported by King Abdullah University of Science and Technology (KAUST).
PublisherAmerican Chemical Society (ACS)
- Review on Non-Volatile Memory with High<i>-k</i> Dielectrics: Flash for Generation Beyond 32 nm.
- Authors: Zhao C, Zhao CZ, Taylor S, Chalker PR
- Issue date: 2014 Jul 15
- Ta<sub>2</sub>O<sub>5</sub>-TiO<sub>2</sub> Composite Charge-trapping Dielectric for the Application of the Nonvolatile Memory.
- Authors: Wei CY, Shen B, Ding P, Han P, Li AD, Xia YD, Xu B, Yin J, Liu ZG
- Issue date: 2017 Jul 20
- The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiO<sub>X</sub> as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide.
- Authors: Park JH, Shin MH, Yi JS
- Issue date: 2019 May 22
- Low temperature below 200 °C solution processed tunable flash memory device without tunneling and blocking layer.
- Authors: Mondal S, Venkataraman V
- Issue date: 2019 May 13
- Fabrication and characterization of twin poly-Si thin film transistors EEPROM with a nitride charge trapping layer.
- Authors: Hung MF, Wu YC, Chiang JH, Chen JH, Chen LC
- Issue date: 2011 Dec