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dc.contributor.authorOmran, Hesham
dc.contributor.authorAlhoshany, Abdulaziz
dc.contributor.authorSalama, Khaled N.
dc.date.accessioned2017-06-13T06:47:11Z
dc.date.available2017-06-13T06:47:11Z
dc.date.issued2017-03-23
dc.date.submitted2015-09-17
dc.identifier.urihttp://hdl.handle.net/10754/624971
dc.description.abstractAn energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog- to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter- based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.
dc.relation.urlhttp://www.google.com/patents/WO2017046782A1
dc.relation.urlhttp://worldwide.espacenet.com/publicationDetails/biblio?CC=WO&NR=2017046782A1&KC=A1&FT=D
dc.titleInverter-based successive approximation capacitance-to-digital converter
dc.typePatent
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
dc.description.statusPublished Application
dc.contributor.assigneeKing Abdullah University Of Science And Technology
dc.description.countryWorld Intellectual Property Organization (WIPO)
dc.identifier.applicationnumberWO 2017046782 A1
refterms.dateFOA2018-06-14T08:26:32Z


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