A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Physical Science and Engineering (PSE) Division
Online Publication Date2016-10-06
Print Publication Date2016-06
Permanent link to this recordhttp://hdl.handle.net/10754/622500
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AbstractWe propose a successive-approximation capacitive sensor readout circuit that achieves 35fJ/Step energy efficiency FoM, which represents 4× improvement over the state-of-the-art. A fully differential architecture is employed to provide robustness against common mode noise and errors. An inverter-based amplifier with near-threshold biasing provides robust, fast, and energy-efficient operation. Quasi-dynamic operation is used to maintain the energy efficiency for a scalable sample rate. A hybrid coarse-fine capacitive DAC achieves 11.7bit effective resolution in a compact area. © 2016 IEEE.
CitationOmran H, Alhoshany A, Alahmadi H, Salama KN (2016) A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation. 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits). Available: http://dx.doi.org/10.1109/VLSIC.2016.7573533.
Conference/Event name30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016