A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation
Type
Conference PaperKAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) DivisionElectrical Engineering Program
Physical Science and Engineering (PSE) Division
Sensors Lab
Date
2016-10-06Online Publication Date
2016-10-06Print Publication Date
2016-06Permanent link to this record
http://hdl.handle.net/10754/622500
Metadata
Show full item recordAbstract
We propose a successive-approximation capacitive sensor readout circuit that achieves 35fJ/Step energy efficiency FoM, which represents 4× improvement over the state-of-the-art. A fully differential architecture is employed to provide robustness against common mode noise and errors. An inverter-based amplifier with near-threshold biasing provides robust, fast, and energy-efficient operation. Quasi-dynamic operation is used to maintain the energy efficiency for a scalable sample rate. A hybrid coarse-fine capacitive DAC achieves 11.7bit effective resolution in a compact area. © 2016 IEEE.Citation
Omran H, Alhoshany A, Alahmadi H, Salama KN (2016) A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation. 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits). Available: http://dx.doi.org/10.1109/VLSIC.2016.7573533.Conference/Event name
30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016Additional Links
http://ieeexplore.ieee.org/document/7573533/ae974a485f413a2113503eed53cd6c53
10.1109/VLSIC.2016.7573533