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dc.contributor.authorOmran, Hesham
dc.contributor.authorAlhoshany, Abdulaziz
dc.contributor.authorAlahmadi, Hamzah
dc.contributor.authorSalama, Khaled N.
dc.date.accessioned2017-01-02T09:55:27Z
dc.date.available2017-01-02T09:55:27Z
dc.date.issued2016-11-16
dc.identifier.citationOmran H, Alhoshany A, Alahmadi H, Salama KN (2016) A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers. IEEE Transactions on Circuits and Systems I: Regular Papers: 1–12. Available: http://dx.doi.org/10.1109/TCSI.2016.2608905.
dc.identifier.issn1549-8328
dc.identifier.issn1558-0806
dc.identifier.doi10.1109/TCSI.2016.2608905
dc.identifier.urihttp://hdl.handle.net/10754/622499
dc.description.abstractA 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.
dc.description.sponsorshipThe authors would like to thank the reviewers for their valuable and stimulating comments.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.relation.urlhttp://ieeexplore.ieee.org/document/7744463/
dc.subjectsuccessive-approximation (SAR)
dc.subjectCapacitance-to-digital converter (CDC)
dc.subjectcapacitive sensor interface circuit
dc.subjectcapacitor array
dc.subjectCMOS
dc.subjectenergyefficient
dc.subjectlow-power
dc.subjectMEMS pressure sensor readout circuit
dc.titleA 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers
dc.typeArticle
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
dc.contributor.departmentElectrical Engineering Program
dc.identifier.journalIEEE Transactions on Circuits and Systems I: Regular Papers
dc.contributor.institutionIntegrated Circuits Lab, Faculty of Engineering, Ain Shams University, Cairo 11566, Egypt.
kaust.personAlhoshany, Abdulaziz
kaust.personAlahmadi, Hamzah
kaust.personSalama, Khaled N.
dc.date.published-online2016-11-16
dc.date.published-print2017-02


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