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    Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

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    Name:
    Aftab_Hussain_PhD_Thesis_FINAL.pdf
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    7.361Mb
    Format:
    PDF
    Description:
    Final Dissertation
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    Type
    Dissertation
    Authors
    Hussain, Aftab M. cc
    Advisors
    Hussain, Muhammad Mustafa cc
    Committee members
    Schwingenschlögl, Udo cc
    Al-Naffouri, Tareq Y. cc
    Li, Xiaohang cc
    Ma, Zhenqiang
    Program
    Electrical Engineering
    KAUST Department
    Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
    Date
    2016-12
    Embargo End Date
    2017-12-01
    Permanent link to this record
    http://hdl.handle.net/10754/621892
    
    Metadata
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    Access Restrictions
    At the time of archiving, the student author of this dissertation opted to temporarily restrict access to it. The full text of this dissertation became available to the public after the expiration of the embargo on 2017-12-01.
    Abstract
    With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We report a process for fabricating through polymer vias (TPVs) facilitating the fabrication of sensor arrays and control electronics on the opposite sides of the same flexible polymer. Finally, we present a process to fabricate stretchable metallic thin films with up to 800% stretchability, and report two distinct applications for these devices which cannot be done using current techniques.
    DOI
    10.25781/KAUST-N757V
    ae974a485f413a2113503eed53cd6c53
    10.25781/KAUST-N757V
    Scopus Count
    Collections
    Dissertations; Dissertations; Electrical Engineering Program; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

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