Experimental verification of on-chip CMOS fractional-order capacitor emulators
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Permanent link to this recordhttp://hdl.handle.net/10754/621648
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AbstractThe experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.
CitationTsirimokou G, Psychalinos C, Salama KN, Elwakil AS (2016) Experimental verification of on-chip CMOS fractional-order capacitor emulators. Electronics Letters 52: 1298–1300. Available: http://dx.doi.org/10.1049/el.2016.1457.