Monolithic 3D CMOS Using Layered Semiconductors
dc.contributor.author | Sachid, Angada B. | |
dc.contributor.author | Tosun, Mahmut | |
dc.contributor.author | Desai, Sujay B. | |
dc.contributor.author | Hsu, Ching-Yi | |
dc.contributor.author | Lien, Der-Hsien | |
dc.contributor.author | Madhvapathy, Surabhi R. | |
dc.contributor.author | Chen, Yu-Ze | |
dc.contributor.author | Hettick, Mark | |
dc.contributor.author | Kang, Jeong Seuk | |
dc.contributor.author | Zeng, Yuping | |
dc.contributor.author | He, Jr-Hau | |
dc.contributor.author | Chang, Edward Yi | |
dc.contributor.author | Chueh, Yu-Lun | |
dc.contributor.author | Javey, Ali | |
dc.contributor.author | Hu, Chenming | |
dc.date.accessioned | 2016-11-03T08:30:49Z | |
dc.date.available | 2016-11-03T08:30:49Z | |
dc.date.issued | 2016-02-02 | |
dc.identifier.citation | Sachid AB, Tosun M, Desai SB, Hsu C-Y, Lien D-H, et al. (2016) Monolithic 3D CMOS Using Layered Semiconductors. Advanced Materials 28: 2547–2554. Available: http://dx.doi.org/10.1002/adma.201505113. | |
dc.identifier.issn | 0935-9648 | |
dc.identifier.pmid | 26833783 | |
dc.identifier.doi | 10.1002/adma.201505113 | |
dc.identifier.uri | http://hdl.handle.net/10754/621498 | |
dc.description.sponsorship | A.B.S. and M.T. contributed equally to this work. A.B.S. and C.H. conceived the idea. A.B.S., M.T., and A.J. formulated the fabrication flow. A.B.S., M.T., S.B.D., C.-Y.H., D.-H.L., S.R.M., M.H., J.S.K., and Y.Z. fabricated the devices. A.B.S. and M.T. performed electrical measurements. A.B.S. analyzed the data. Y.-Z.C. and Y.-L.C. did transmission electron microscopy. All the authors were involved in preparing the manuscript. A.B.S. was funded by Applied Materials, Inc. and Entegris, Inc. under the I-RiCE Program. M.T. was funded by the Director, Office of Science, Office of Basic Energy Sciences, and Materials Sciences and Engineering Division of the U.S. Department of Energy under Contract No. DE-AC02-05Ch11231. | |
dc.publisher | Wiley | |
dc.subject | Metal oxide semiconductors | |
dc.subject | Monolithic 3D integration | |
dc.subject | Transition metal dichalcogenides | |
dc.subject | Ultra-low voltage operation | |
dc.title | Monolithic 3D CMOS Using Layered Semiconductors | |
dc.type | Article | |
dc.contributor.department | Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division | |
dc.contributor.department | Electrical Engineering Program | |
dc.contributor.department | KAUST Solar Center (KSC) | |
dc.identifier.journal | Advanced Materials | |
dc.contributor.institution | Electrical Engineering and Computer Sciences; University of California; Berkeley CA 94720 USA | |
dc.contributor.institution | Material Sciences Division; Lawrence Berkeley National Laboratory; Berkeley CA 94720 USA | |
dc.contributor.institution | Berkeley Sensor and Actuator Center; University of California; Berkeley CA 94720 USA | |
dc.contributor.institution | Department of Material Sciences and Engineering; National Chao-Tung University; Hsinchu 300 Taiwan | |
dc.contributor.institution | Department of Materials Science and Engineering; National Tsing Hua University; Hsinchu 30013 Taiwan | |
dc.contributor.institution | Joint Center for Artificial Photosynthesis; Lawrence Berkeley National Laboratory; Berkeley CA 94720 USA | |
kaust.person | Lien, Der-Hsien | |
kaust.person | He, Jr-Hau | |
dc.date.published-online | 2016-02-02 | |
dc.date.published-print | 2016-04 |
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Articles
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Electrical Engineering Program
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KAUST Solar Center (KSC)
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Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
For more information visit: https://cemse.kaust.edu.sa/