AuthorsSachid, Angada B.
Desai, Sujay B.
Madhvapathy, Surabhi R.
Kang, Jeong Seuk
Chang, Edward Yi
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
KAUST Solar Center (KSC)
Online Publication Date2016-02-02
Print Publication Date2016-04
Permanent link to this recordhttp://hdl.handle.net/10754/621498
MetadataShow full item record
CitationSachid AB, Tosun M, Desai SB, Hsu C-Y, Lien D-H, et al. (2016) Monolithic 3D CMOS Using Layered Semiconductors. Advanced Materials 28: 2547–2554. Available: http://dx.doi.org/10.1002/adma.201505113.
SponsorsA.B.S. and M.T. contributed equally to this work. A.B.S. and C.H. conceived the idea. A.B.S., M.T., and A.J. formulated the fabrication flow. A.B.S., M.T., S.B.D., C.-Y.H., D.-H.L., S.R.M., M.H., J.S.K., and Y.Z. fabricated the devices. A.B.S. and M.T. performed electrical measurements. A.B.S. analyzed the data. Y.-Z.C. and Y.-L.C. did transmission electron microscopy. All the authors were involved in preparing the manuscript. A.B.S. was funded by Applied Materials, Inc. and Entegris, Inc. under the I-RiCE Program. M.T. was funded by the Director, Office of Science, Office of Basic Energy Sciences, and Materials Sciences and Engineering Division of the U.S. Department of Energy under Contract No. DE-AC02-05Ch11231.
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