Monolithic 3D CMOS Using Layered Semiconductors

Type
Article
Authors
Sachid, Angada B.
Tosun, Mahmut
Desai, Sujay B.
Hsu, Ching-Yi
Lien, Der-Hsien cc
Madhvapathy, Surabhi R.
Chen, Yu-Ze
Hettick, Mark
Kang, Jeong Seuk
Zeng, Yuping
He, Jr-Hau cc
Chang, Edward Yi
Chueh, Yu-Lun
Javey, Ali
Hu, Chenming
KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
KAUST Solar Center (KSC)
Date
2016-02-02
Online Publication Date
2016-02-02
Print Publication Date
2016-04
Permanent link to this record
http://hdl.handle.net/10754/621498

Metadata
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Citation
Sachid AB, Tosun M, Desai SB, Hsu C-Y, Lien D-H, et al. (2016) Monolithic 3D CMOS Using Layered Semiconductors. Advanced Materials 28: 2547–2554. Available: http://dx.doi.org/10.1002/adma.201505113.
Sponsors
A.B.S. and M.T. contributed equally to this work. A.B.S. and C.H. conceived the idea. A.B.S., M.T., and A.J. formulated the fabrication flow. A.B.S., M.T., S.B.D., C.-Y.H., D.-H.L., S.R.M., M.H., J.S.K., and Y.Z. fabricated the devices. A.B.S. and M.T. performed electrical measurements. A.B.S. analyzed the data. Y.-Z.C. and Y.-L.C. did transmission electron microscopy. All the authors were involved in preparing the manuscript. A.B.S. was funded by Applied Materials, Inc. and Entegris, Inc. under the I-RiCE Program. M.T. was funded by the Director, Office of Science, Office of Basic Energy Sciences, and Materials Sciences and Engineering Division of the U.S. Department of Energy under Contract No. DE-AC02-05Ch11231.
Publisher
Wiley
Journal
Advanced Materials
DOI
10.1002/adma.201505113
PubMed ID
26833783
Collections
Articles; Electrical and Computer Engineering Program; KAUST Solar Center (KSC); Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division