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    Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

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    Name:
    Fina Thesis_Back End of Line Nanorelays - JavierLechuga.pdf
    Size:
    9.285Mb
    Format:
    PDF
    Description:
    Final Thesis
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    Type
    Thesis
    Authors
    Lechuga Aranda, Jesus Javier cc
    Advisors
    Fariborzi, Hossein cc
    Committee members
    Salama, Khaled N. cc
    Younis, Mohammad I. cc
    Program
    Electrical and Computer Engineering
    KAUST Department
    Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division
    Date
    2016-05
    Embargo End Date
    2017-05-17
    Permanent link to this record
    http://hdl.handle.net/10754/609468
    
    Metadata
    Show full item record
    Access Restrictions
    At the time of archiving, the student author of this thesis opted to temporarily restrict access to it. The full text of this thesis became available to the public after the expiration of the embargo on 2017-05-17.
    Abstract
    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of devices. To verify the performance of the proposed model, complex logic circuits built exclusively with relays, and also, hybrid CMOS-NEM circuits are simulated and verified. Finally, these novel topologies are reviewed and discussed as low-power alternatives to current CMOS topologies.
    Citation
    Lechuga Aranda, J. J. (2016). Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits. KAUST Research Repository. https://doi.org/10.25781/KAUST-678Y8
    DOI
    10.25781/KAUST-678Y8
    ae974a485f413a2113503eed53cd6c53
    10.25781/KAUST-678Y8
    Scopus Count
    Collections
    MS Theses; Electrical and Computer Engineering Program; Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division

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