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dc.contributor.authorDeftu, A.
dc.contributor.authorMurarasu, A.
dc.date.accessioned2016-02-25T13:52:55Z
dc.date.available2016-02-25T13:52:55Z
dc.date.issued2013-02
dc.identifier.citationDeftu A, Murarasu A (2013) Optimization Techniques for Dimensionally Truncated Sparse Grids on Heterogeneous Systems. 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. Available: http://dx.doi.org/10.1109/PDP.2013.57.
dc.identifier.doi10.1109/PDP.2013.57
dc.identifier.urihttp://hdl.handle.net/10754/599103
dc.description.abstractGiven the existing heterogeneous processor landscape dominated by CPUs and GPUs, topics such as programming productivity and performance portability have become increasingly important. In this context, an important question refers to how can we develop optimization strategies that cover both CPUs and GPUs. We answer this for fastsg, a library that provides functionality for handling efficiently high-dimensional functions. As it can be employed for compressing and decompressing large-scale simulation data, it finds itself at the core of a computational steering application which serves us as test case. We describe our experience with implementing fastsg's time critical routines for Intel CPUs and Nvidia Fermi GPUs. We show the differences and especially the similarities between our optimization strategies for the two architectures. With regard to our test case for which achieving high speedups is a "must" for real-time visualization, we report a speedup of up to 6.2x times compared to the state-of-the-art implementation of the sparse grid technique for GPUs. © 2013 IEEE.
dc.description.sponsorshipThis publication is based on work supported by Award No.UK-C0020, made by King Abdullah University of Science andTechnology (KAUST).
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectCUDA
dc.subjectGPU
dc.subjectlibrary
dc.subjectoptimizations
dc.subjectsparse grids
dc.titleOptimization Techniques for Dimensionally Truncated Sparse Grids on Heterogeneous Systems
dc.typeConference Paper
dc.identifier.journal2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
dc.contributor.institutionTechnische Universitat Munchen, Munich, Germany
kaust.grant.numberUK-C0020


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