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dc.contributor.authorLi, Jingqi
dc.date.accessioned2016-02-04T13:29:55Z
dc.date.available2016-02-04T13:29:55Z
dc.date.issued2015-11-19
dc.date.submitted2015-05-13
dc.identifier.urihttp://hdl.handle.net/10754/595584
dc.description.abstractEmbodiments of the present disclosure provide for vertically aligned CNTFET, methods of making vertically aligned CNTFET, methods of using vertically aligned CNTFET, and the like.
dc.relation.urlhttp://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220150333282%22.PGNR.&OS=DN/20150333282&RS=DN/20150333282
dc.relation.urlhttp://assignment.uspto.gov/#/search?adv=publNum:20150333282
dc.relation.urlhttp://www.google.com/patents/US20150333282
dc.relation.urlhttp://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=2015333282A1&KC=A1&FT=D
dc.titleMethods and devices for silicon integrated vertically aligned field effect transistors
dc.typePatent
dc.contributor.departmentAdvanced Nanofabrication and Thin Film Core Lab
dc.description.statusGranted Patent
dc.contributor.assigneeKing Abdullah University of Science and Technology
dc.description.countryUnited States
dc.identifier.patentnumberUS9318718B2
dc.identifier.applicationnumberUS 20150333282 A1
refterms.dateFOA2018-06-13T11:57:53Z


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