Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration
Type
ArticleAuthors
Pirro, Luca
Diab, Amer El Hajj
Ionica, Irina
Ghibaudo, Gerard
Faraone, Lorenzo
Cristoloveanu, Sorin
KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) DivisionElectrical Engineering Program
Integrated Nanotechnology Lab
Date
2015-09Permanent link to this record
http://hdl.handle.net/10754/594194
Metadata
Show full item recordAbstract
Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.Citation
Pirro L, Diab A, Ionica I, Ghibaudo G, Faraone L, et al. (2015) Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration. IEEE Transactions on Electron Devices 62: 2717–2723. Available: http://dx.doi.org/10.1109/ted.2015.2454438.Sponsors
Soitec, Bernin, FranceEuropean ENIAC Projects Places2be
ae974a485f413a2113503eed53cd6c53
10.1109/ted.2015.2454438