Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration
Diab, Amer El Hajj
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Integrated Nanotechnology Lab
Permanent link to this recordhttp://hdl.handle.net/10754/594194
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AbstractRecent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.
CitationPirro L, Diab A, Ionica I, Ghibaudo G, Faraone L, et al. (2015) Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration. IEEE Transactions on Electron Devices 62: 2717–2723. Available: http://dx.doi.org/10.1109/ted.2015.2454438.
SponsorsSoitec, Bernin, France
European ENIAC Projects Places2be