Type
Book ChapterAuthors
Hussain, Muhammad Mustafa
Shamiryan, Denis G.
Paraschiv, Vasile
Sano, Kenichi
Reinhardt, Karen A.
KAUST Department
Electrical Engineering ProgramIntegrated Nanotechnology Lab
Physical Science and Engineering (PSE) Division
Date
2011-02-22Permanent link to this record
http://hdl.handle.net/10754/575837
Metadata
Show full item recordAbstract
High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.Citation
Hussain, M. M., Shamiryan, D., Paraschiv, V., Sano, K., & Reinhardt, K. A. (2011). Cleaning Challenges of High-κ/Metal Gate Structures. Handbook of Cleaning in Semiconductor Manufacturing, 237–284. doi:10.1002/9781118071748.ch7Publisher
WileyISBN
9780470625958ae974a485f413a2113503eed53cd6c53
10.1002/9781118071748.ch7