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    High performance matrix inversion based on LU factorization for multicore architectures

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    Type
    Conference Paper
    Authors
    Dongarra, Jack
    Faverge, Mathieu
    Ltaief, Hatem cc
    Luszczek, Piotr R.
    KAUST Department
    Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
    Extreme Computing Research Center
    KAUST Supercomputing Laboratory (KSL)
    Date
    2011
    Permanent link to this record
    http://hdl.handle.net/10754/575750
    
    Metadata
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    Abstract
    The goal of this paper is to present an efficient implementation of an explicit matrix inversion of general square matrices on multicore computer architecture. The inversion procedure is split into four steps: 1) computing the LU factorization, 2) inverting the upper triangular U factor, 3) solving a linear system, whose solution yields inverse of the original matrix and 4) applying backward column pivoting on the inverted matrix. Using a tile data layout, which represents the matrix in the system memory with an optimized cache-aware format, the computation of the four steps is decomposed into computational tasks. A directed acyclic graph is generated on the fly which represents the program data flow. Its nodes represent tasks and edges the data dependencies between them. Previous implementations of matrix inversions, available in the state-of-the-art numerical libraries, are suffer from unnecessary synchronization points, which are non-existent in our implementation in order to fully exploit the parallelism of the underlying hardware. Our algorithmic approach allows to remove these bottlenecks and to execute the tasks with loose synchronization. A runtime environment system called QUARK is necessary to dynamically schedule our numerical kernels on the available processing units. The reported results from our LU-based matrix inversion implementation significantly outperform the state-of-the-art numerical libraries such as LAPACK (5x), MKL (5x) and ScaLAPACK (2.5x) on a contemporary AMD platform with four sockets and the total of 48 cores for a matrix of size 24000. A power consumption analysis shows that our high performance implementation is also energy efficient and substantially consumes less power than its competitors. © 2011 ACM.
    Publisher
    Association for Computing Machinery (ACM)
    Journal
    Proceedings of the 2011 ACM international workshop on Many task computing on grids and supercomputers - MTAGS '11
    Conference/Event name
    Proceedings of the 2011 ACM international workshop on Many task computing on grids and supercomputers
    ISBN
    9781450311458
    DOI
    10.1145/2132876.2132885
    ae974a485f413a2113503eed53cd6c53
    10.1145/2132876.2132885
    Scopus Count
    Collections
    Conference Papers; KAUST Supercomputing Laboratory (KSL); Extreme Computing Research Center; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

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