KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Online Publication Date2015-08-17
Print Publication Date2016-02
Permanent link to this recordhttp://hdl.handle.net/10754/575242
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AbstractReducing the capacitance of programmable capacitor arrays, commonly used in analog integrated circuits, is necessary for low-energy applications. However, limited mismatch data is available for small capacitors. We report mismatch measurement for a 2fF poly-insulator-poly (PIP) capacitor, which is the smallest reported PIP capacitor to the best of the authors’ knowledge. Instead of using complicated custom onchip circuitry, direct mismatch measurement is demonstrated and verified using Monte Carlo Simulations and experimental measurements. Capacitive test structures composed of 9-bit programmable capacitor arrays (PCAs) are implemented in a low-cost 0:35m CMOS process. Measured data is compared to mismatch of large PIP capacitors, theoretical models, and recently published data. Measurement results indicate an estimated average relative standard deviation of 0.43% for the 2fF unit capacitor, which is better than the reported mismatch of metal-oxide-metal (MOM) fringing capacitors implemented in an advanced 32nm CMOS process.
CitationDirect Mismatch Characterization of femto-Farad Capacitors 2015:1 IEEE Transactions on Circuits and Systems II: Express Briefs