Tin (Sn) for enhancing performance in silicon CMOS

Type
Conference Paper
Authors
Hussain, Aftab M. cc
Fahad, Hossain M.
Singh, Nirpendra cc
Sevilla, Galo T. cc
Schwingenschlögl, Udo cc
Hussain, Muhammad Mustafa cc
KAUST Department
Computational Physics and Materials Science (CPMS)
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Integrated Nanotechnology Lab
Material Science and Engineering Program
Physical Science and Engineering (PSE) Division
Date
2013-10
Permanent link to this record
http://hdl.handle.net/10754/564809

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Abstract
We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.
Citation
Hussain, A. M., Fahad, H. M., Singh, N., Torres Sevilla, G. A., Schwingenschlogl, U., & Hussain, M. M. (2013). Tin (Sn) for enhancing performance in silicon CMOS. 2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC). doi:10.1109/nmdc.2013.6707470
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Journal
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)
Conference/Event name
2013 IEEE 8th Nanotechnology Materials and Devices Conference, IEEE NMDC 2013
ISBN
9781479933877
DOI
10.1109/NMDC.2013.6707470
Collections
Conference Papers; Physical Science and Engineering (PSE) Division; Electrical Engineering Program; Material Science and Engineering Program; Integrated Nanotechnology Lab; Computational Physics and Materials Science (CPMS); Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division