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Hardware realization of chaos based block cipher for image encryption

dc.contributor.authorBarakat, Mohamed L.
dc.contributor.authorRadwan, Ahmed G.
dc.contributor.authorSalama, Khaled N.
dc.date.accessioned2015-08-04T07:01:57Z
dc.date.available2015-08-04T07:01:57Z
dc.date.issued2011-12
dc.identifier.isbn9781457722073
dc.identifier.doi10.1109/ICM.2011.6177386
dc.identifier.urihttp://hdl.handle.net/10754/564475
dc.description.abstractUnlike stream ciphers, block ciphers are very essential for parallel processing applications. In this paper, the first hardware realization of chaotic-based block cipher is proposed for image encryption applications. The proposed system is tested for known cryptanalysis attacks and for different block sizes. When implemented on Virtex-IV, system performance showed high throughput and utilized small area. Passing successfully in all tests, our system proved to be secure with all block sizes. © 2011 IEEE.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.titleHardware realization of chaos based block cipher for image encryption
dc.typeConference Paper
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
dc.contributor.departmentElectrical Engineering Program
dc.contributor.departmentPhysical Science and Engineering (PSE) Division
dc.contributor.departmentSensors Lab
dc.identifier.journalICM 2011 Proceeding
dc.conference.date19 December 2011 through 22 December 2011
dc.conference.name2011 23rd International Conference on Microelectronics, ICM 2011
dc.conference.locationHammamet
dc.contributor.institutionElectrical Engineering Program, Applied Engineering Mathematics, Cairo University, Egypt
kaust.personBarakat, Mohamed L.
kaust.personRadwan, Ahmed G.
kaust.personSalama, Khaled N.


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