Hardware realization of chaos based block cipher for image encryption
KAUST DepartmentElectrical Engineering Program
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Physical Sciences and Engineering (PSE) Division
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AbstractUnlike stream ciphers, block ciphers are very essential for parallel processing applications. In this paper, the first hardware realization of chaotic-based block cipher is proposed for image encryption applications. The proposed system is tested for known cryptanalysis attacks and for different block sizes. When implemented on Virtex-IV, system performance showed high throughput and utilized small area. Passing successfully in all tests, our system proved to be secure with all block sizes. © 2011 IEEE.
JournalICM 2011 Proceeding
Conference/Event name2011 23rd International Conference on Microelectronics, ICM 2011