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dc.contributor.authorOmran, Hesham
dc.contributor.authorSharaf, Khaled M W
dc.contributor.authorIbrahim, Magdi Marzouk
dc.date.accessioned2015-08-04T06:26:32Z
dc.date.available2015-08-04T06:26:32Z
dc.date.issued2011-08
dc.identifier.citationOmran, H., Sharaf, K., & Ibrahim, M. (2011). A low-power digital frequency divider for system-on-a-chip applications. 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). doi:10.1109/mwscas.2011.6026674
dc.identifier.isbn9781612848570
dc.identifier.issn15483746
dc.identifier.doi10.1109/MWSCAS.2011.6026674
dc.identifier.urihttp://hdl.handle.net/10754/564406
dc.description.abstractIn this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.titleA low-power digital frequency divider for system-on-a-chip applications
dc.typeConference Paper
dc.contributor.departmentElectrical Engineering Program
dc.identifier.journal2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
dc.conference.date7 August 2011 through 10 August 2011
dc.conference.name54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
dc.conference.locationSeoul
dc.contributor.institutionElectronics and Communications Engineering Department, Faculty of Engineering, Ain Shams University, Cairo, Egypt
kaust.personOmran, Hesham


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