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    A low-power digital frequency divider for system-on-a-chip applications

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    Type
    Conference Paper
    Authors
    Omran, Hesham cc
    Sharaf, Khaled M W
    Ibrahim, Magdi Marzouk
    KAUST Department
    Electrical Engineering Program
    Date
    2011-08
    Permanent link to this record
    http://hdl.handle.net/10754/564406
    
    Metadata
    Show full item record
    Abstract
    In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.
    Citation
    Omran, H., Sharaf, K., & Ibrahim, M. (2011). A low-power digital frequency divider for system-on-a-chip applications. 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). doi:10.1109/mwscas.2011.6026674
    Publisher
    Institute of Electrical and Electronics Engineers (IEEE)
    Journal
    2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
    Conference/Event name
    54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
    ISBN
    9781612848570
    DOI
    10.1109/MWSCAS.2011.6026674
    ae974a485f413a2113503eed53cd6c53
    10.1109/MWSCAS.2011.6026674
    Scopus Count
    Collections
    Conference Papers; Electrical and Computer Engineering Program

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