A low-power digital frequency divider for system-on-a-chip applications
Type
Conference PaperKAUST Department
Electrical Engineering ProgramDate
2011-08Permanent link to this record
http://hdl.handle.net/10754/564406
Metadata
Show full item recordAbstract
In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.Citation
Omran, H., Sharaf, K., & Ibrahim, M. (2011). A low-power digital frequency divider for system-on-a-chip applications. 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). doi:10.1109/mwscas.2011.6026674Conference/Event name
54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011ISBN
9781612848570ae974a485f413a2113503eed53cd6c53
10.1109/MWSCAS.2011.6026674