Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt
AuthorsHinkle, Christopher L.
Galatage, Rohit V.
Chapman, Richard A.
Vogel, Eric M.
Alshareef, Husam N.
Freeman, Clive M.
Li-Fatou, Andrei V.
Shaw, Judy B.
Chambers, James J.
KAUST DepartmentPhysical Sciences and Engineering (PSE) Division
Materials Science and Engineering Program
Functional Nanomaterials and Devices Research Group
Permanent link to this recordhttp://hdl.handle.net/10754/564284
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AbstractIn this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.
Conference/Event name2010 Symposium on VLSI Technology, VLSIT 2010