Flexible and transparent silicon-on-polymer based sub-20 nm non-planar 3D FinFET for brain-architecture inspired computation

Type
Article
Authors
Sevilla, Galo T. cc
Rojas, Jhonathan Prieto cc
Fahad, Hossain M.
Hussain, Aftab M. cc
Ghanem, Rawan cc
Smith, Casey
Hussain, Muhammad Mustafa cc
KAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Integrated Nanotechnology Lab
Physical Science and Engineering (PSE) Division
The KAUST School
KAUST Grant Number
CRG-1-2012-HUS-008
Date
2014-02-22
Online Publication Date
2014-02-22
Print Publication Date
2014-05
Permanent link to this record
http://hdl.handle.net/10754/563402

Metadata
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Abstract
An industry standard 8′′ silicon-on-insulator wafer based ultra-thin (1 μm), ultra-light-weight, fully flexible and remarkably transparent state-of-the-art non-planar three dimensional (3D) FinFET is shown. Introduced by Intel Corporation in 2011 as the most advanced transistor architecture, it reveals sub-20 nm features and the highest performance ever reported for a flexible transistor. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Sponsors
We would like to thank the Competitive Research Grant: CRG-1-2012-HUS-008 and the staff of the KAUST Advanced Nanofabrication Facilities for their technical support during the development of this project. We also thank Dr. Casey Smith for mask design. We are also grateful to Maria Peredo Silva for the rendition of Figure 2. Finally we thank Mrs. Kelly Rader for proof reading our revised manuscript.
Publisher
Wiley-VCH Verlag
Journal
Advanced Materials
DOI
10.1002/adma.201305309
10.1002/adma.201470116
Collections
Articles; Physical Science and Engineering (PSE) Division; Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division