Hardware stream cipher with controllable chaos generator for colour image encryption
Type
ArticleKAUST Department
Electrical Engineering ProgramComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Sensors Lab
Date
2014-01-01Permanent link to this record
http://hdl.handle.net/10754/563320
Metadata
Show full item recordAbstract
This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s. © The Institution of Engineering and Technology 2013.Citation
Barakat, M. L., Mansingka, A. S., Radwan, A. G., & Salama, K. N. (2014). Hardware stream cipher with controllable chaos generator for colour image encryption. IET Image Processing, 8(1), 33–43. doi:10.1049/iet-ipr.2012.0586Journal
IET Image Processingae974a485f413a2113503eed53cd6c53
10.1049/iet-ipr.2012.0586