High-performance silicon nanotube tunneling FET for ultralow-power logic applications
KAUST DepartmentElectrical Engineering Program
Integrated Nanotechnology Lab
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Permanent link to this recordhttp://hdl.handle.net/10754/562674
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AbstractTo increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.
CitationFahad, H. M., & Hussain, M. M. (2013). High-Performance Silicon Nanotube Tunneling FET for Ultralow-Power Logic Applications. IEEE Transactions on Electron Devices, 60(3), 1034–1039. doi:10.1109/ted.2013.2243151
SponsorsThis work was supported by the Office of Sponsored Research at King Abdullah University of Science and Technology under Competitive Research Grant CRG-1-2012-HUS-008. The review of this paper was arranged by Editor W. Tsai.