In this paper, we study the design parameters of capacitive interdigitated electrodes (IDEs) and the effect of these parameters on the sensitivity of the IDEs when employed as a capacitive gas sensor. Finite element simulations using COMSOL Multiphysics were carried out to evaluate the sensitivity of the capacitive sensor. Simulations show that for permittivity-based sensing, the optimum thickness of the sensing film is slightly more than half the wavelength of the IDEs structure. On the other hand, sensing films that are thinner than half wavelength should be used if the required sensing mechanism is based on structural swelling. Increasing the IDEs metal thickness can increase the sensitivity by increasing the sidewall electric field, but this is only true if the sensing film is thick enough to completely fill the spacing between the electrodes. A simple and reliable IDEs structure and fabrication process are proposed. Physical dry etching provides good yield and fine resolution compared to liftoff technique. Fabricated and packaged prototype sensors are presented. © 2015 IEEE.

We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

We report an agglutination-based immunosensor for the quantification of C-reactive protein (CRP). The developed immunoassay sensor requires approximately 15 minutes of assay time per sample and provides a sensitivity of 0.5 mg/L. We have measured the capacitance of interdigitated electrodes (IDEs) and quantified the concentration of added analyte. The proposed method is a label free detection method and hence provides rapid measurement preferable in diagnostics. We have so far been able to quantify the concentration to as low as 0.5 mg/L and as high as 10 mg/L. By quantifying CRP in serum, we can assess whether patients are prone to cardiac diseases and monitor the risk associated with such diseases. The sensor is a simple low cost structure and it can be a promising device for rapid and sensitive detection of disease markers at the point-of-care stage.

A prototypical metal-organic framework (MOF), a 2D periodic porous structure based on the assembly of copper ions and benzene dicarboxylate (bdc) ligands (Cu(bdc)·xH2O), was grown successfully as a thin film on interdigitated electrodes (IDEs). IDEs have been used for achieving planar CMOS-compatible low-cost capacitive sensing structures for the detection of humidity and volatile organic compounds (VOCs). Accordingly, the resultant IDEs coated with the Cu(bdc)·xH2O thin film was evaluated, for the first time, as a capacitive sensor for gas sensing applications. A fully automated setup, using LabVIEW interfaces to experiment conduction and data acquisition, was developed in order to measure the associated gas sensing performance.

Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array.

In this paper, we present a capacitive sensor digital interface circuit using true capacitance-domain successive approximation that is independent of supply voltage. Robust operation is achieved by using a charge amplifier stage and multiple comparison technique. The interface circuit is insensitive to parasitic capacitances, offset voltages, and charge injection, and is not prone to noise coupling. The proposed design achieves very low temperature sensitivity of 25ppm/oC. A coarse-fine programmable capacitance array allows digitizing a wide capacitance range of 16pF with 12.5-bit quantization limited resolution in a compact area of 0.07mm2. The fabricated prototype is experimentally verified using on-chip sensor and off-chip MEMS capacitive pressure sensor. © 2014 IEEE.

In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

In this paper, we propose an energy-efficient 13-bit capacitive sensor interface circuit. The proposed design fully relies on successive approximation algorithm, which eliminates the need for oversampling and digital decimation filtering, and thus low-power consumption is achieved. The proposed architecture employs a charge amplifier stage to acheive parasitic insensitive operation and fine absolute resolution. Moreover, the output code is not affected by offset voltages or charge injection. The successive approximation algorithm is implemented in the capacitance-domain using a coarse-fine programmable capacitor array, which allows digitizing wide capacitance range in compact area. Analysis for the maximum achievable resolution due to mismatch is provided. The proposed design is insensitive to any reference voltage or current which translates to low temperature sensitivity. The operation of a prototype fabricated in a standard CMOS technology is experimentally verified using both on-chip and off-chip capacitive sensors. Compared to similar prior work, the fabricated prototype achieves and excellent energy efficiency of 34 pJ/step.

In this paper, we present for the first time a family of memristor-based reactance-less oscillators (MRLOs). The proposed oscillators require no reactive components, that is, inductors or capacitors, rather, the ‘resistance storage’ property of memristor is exploited to generate the oscillation. Different types of MRLO family are presented, and for each type, closed form expressions are derived for the oscillation condition, oscillation frequency, and range of oscillation. Derived equations are further verified using transient circuit simulations. A comparison between different MRLO types is also discussed. In addition, detailed fabrication steps of a memristor device and experimental results for the first MRLO physical realization are presented.