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Low pull-in voltage electrostatic MEMS switch using liquid dielectric
(2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), Institute of Electrical and Electronics Engineers (IEEE), 2014-08) [Conference Paper]
In this paper, we present an electrostatic MEMS switch with liquids as dielectric to reduce the actuation voltage. The concept is verified by simulating a lateral dual gate switch, where the required pull-in voltage is reduced by more than 8 times after using water as a dielectric, to become as low as 5.36V. The proposed switch is simulated using COMSOL multiphysics using various liquid volumes to study their effect on the switching performance. Finally, we propose the usage of the lateral switch as a single switch XOR logic gate.
Foldable neuromorphic memristive electronics
(2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Institute of Electrical and Electronics Engineers (IEEE), 2014-07) [Conference Paper]
Neuromorphic computer will need folded architectural form factor to match brain cortex's folded pattern for ultra-compact design. In this work, we show a state-of-the-art CMOS compatible pragmatic fabrication approach of building structurally foldable and densely integrated neuromorphic devices for non-volatile memory applications. We report the first ever memristive devices with the size of a motor neuron on bulk mono-crystalline silicon (100) and then with trench-protect-release-recycle process transform the silicon wafer with devices into a flexible and semi-transparent silicon fabric while recycling the remaining wafer for further use. This process unconditionally offers the ultra-large-scale-integration opportunity-increasingly critical for ultra-compact memory.
Memristor based crossbar memory array sneak path estimation
(2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Institute of Electrical and Electronics Engineers (IEEE), 2014-07) [Conference Paper]
Gateless Memristor Arrays have the advantage of offering high density systems however; their main limitation is the current leakage or the sneak path. Several techniques have been used to address this problem, mainly concentrating on spatial and temporal solutions in setting a dynamic threshold. In this paper, a novel approach is used in terms of utilizing channel estimation and detection theory, primarily building on OFDM concepts of pilot settings, to actually benefit from prior read values in estimating the noise level and utilizing it to further enhance the reliability and accuracy of the read out process.
Leakage analysis of crossbar memristor arrays
(2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Institute of Electrical and Electronics Engineers (IEEE), 2014-07) [Conference Paper]
Crossbar memristor arrays provide a promising high density alternative for the current memory and storage technologies. These arrays suffer from parasitic current components that significantly increase the power consumption, and could ruin the readout operation. In this work we study the trade-off between the crossbar array density and the power consumption required for its readout. Our analysis is based on simulating full memristor arrays on a SPICE platform.
Towards neuromorphic electronics: Memristors on foldable silicon fabric
(Microelectronics Journal, Elsevier BV, 2014-11) [Article]
The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex's folded pattern for ultra-compact design.