Zidan, Mohammed A.; Eltawil, Ahmed M.; Fahmy, Hossam A.H.; Kurdahi, Fadi; Salama, Khaled N.(IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers (IEEE), 2014-06-18)[Article]
In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings. The new method requires fewer reading steps compared to previously reported techniques, and has a very small impact on the memory density. To verify the underlying theory, the proposed system is simulated using Synopsys HSPICE showing the ability to achieve a 100% sneak-path error-free memory. In addition, the effect of quantization bits on the system performance is studied.
Mansingka, Abhinav S.; Zidan, Mohammed A.; Barakat, Mohamed L.; Radwan, Ahmed Gomaa; Salama, Khaled N.(Microelectronics Journal, Elsevier BV, 2014-06-18)[Article]
This paper introduces fully digital implementations of four di erent systems in the 3rd order jerk-equation based chaotic family
using the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal or
chaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations between
two system implementations of different bus widths, with up to 100x higher maximum Lyapunov exponent than the original jerkequation
based chaotic systems. The resulting chaotic output is shown to pass the NIST sp. 800-22 statistical test suite for pseudorandom
number generators without post-processing by only eliminating the statistically defective bits. The systems are designed
in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59 Gbits/s for the native
chaotic output and 8.77 Gbits/s for the resulting pseudo-random number generators.
Mansingka, Abhinav S.; Radwan, Ahmed Gomaa; Salama, Khaled N.; Zidan, Mohammed A.(2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Institute of Electrical and Electronics Engineers (IEEE), 2014-06-18)[Conference Paper]
This paper introduces a generalized fully digital
hardware implementation of 1-D, 2-D and 3-D multiscroll chaos
through sawtooth nonlinearities in a 3rd order ODE with the
Euler approximation, wherein low-significance bits pass all NIST
SP. 800-22 tests. The low-significance bits show good performance
as spreading code for multiple-access DS-CDMA in AWGN and
multipath environments, equivalent to Gold codes. This system
capitalizes on complex nonlinear dynamics afforded by multiscroll
chaos to provide higher security than conventional codes
with the same BER performance demonstrated experimentally
on a Xilinx Virtex 4 FPGA with logic utilization less than 1.25%
and throughput up to 10.92 Gbits/s.
Radwan, Ahmed Gomaa; Mansingka, Abhinav S.; Salama, Khaled N.; Zidan, Mohammed A.(2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), Institute of Electrical and Electronics Engineers (IEEE), 2014-06-18)[Conference Paper]
This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.
Zidan, Mohammed A.; Kosel, Jürgen; Salama, Khaled N.(2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), Institute of Electrical and Electronics Engineers (IEEE), 2014-08)[Conference Paper]
In this paper, we present an electrostatic MEMS switch with liquids as dielectric to reduce the actuation voltage. The concept is verified by simulating a lateral dual gate switch, where the required pull-in voltage is reduced by more than 8 times after using water as a dielectric, to become as low as 5.36V. The proposed switch is simulated using COMSOL multiphysics using various liquid volumes to study their effect on the switching performance. Finally, we propose the usage of the lateral switch as a single switch XOR logic gate.
Ghoneim, Mohamed T.; Zidan, Mohammed A.; Salama, Khaled N.; Hussain, Muhammad Mustafa(2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Institute of Electrical and Electronics Engineers (IEEE), 2014-07)[Conference Paper]
Neuromorphic computer will need folded architectural form factor to match brain cortex's folded pattern for ultra-compact design. In this work, we show a state-of-the-art CMOS compatible pragmatic fabrication approach of building structurally foldable and densely integrated neuromorphic devices for non-volatile memory applications. We report the first ever memristive devices with the size of a motor neuron on bulk mono-crystalline silicon (100) and then with trench-protect-release-recycle process transform the silicon wafer with devices into a flexible and semi-transparent silicon fabric while recycling the remaining wafer for further use. This process unconditionally offers the ultra-large-scale-integration opportunity-increasingly critical for ultra-compact memory.
Naous, Rawan; Zidan, Mohammed A.; Salem, Ahmed Sultan; Salama, Khaled N.(2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Institute of Electrical and Electronics Engineers (IEEE), 2014-07)[Conference Paper]
Gateless Memristor Arrays have the advantage of offering high density systems however; their main limitation is the current leakage or the sneak path. Several techniques have been used to address this problem, mainly concentrating on spatial and temporal solutions in setting a dynamic threshold. In this paper, a novel approach is used in terms of utilizing channel estimation and detection theory, primarily building on OFDM concepts of pilot settings, to actually benefit from prior read values in estimating the noise level and utilizing it to further enhance the reliability and accuracy of the read out process.
Zidan, Mohammed A.; Salem, Ahmed Sultan; Fahmy, Hossam Aly Hassan; Salama, Khaled N.(2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Institute of Electrical and Electronics Engineers (IEEE), 2014-07)[Conference Paper]
Crossbar memristor arrays provide a promising high density alternative for the current memory and storage technologies. These arrays suffer from parasitic current components that significantly increase the power consumption, and could ruin the readout operation. In this work we study the trade-off between the crossbar array density and the power consumption required for its readout. Our analysis is based on simulating full memristor arrays on a SPICE platform.
Ghoneim, Mohamed T.; Zidan, Mohammed A.; Salama, Khaled N.; Hussain, Muhammad Mustafa(Microelectronics Journal, Elsevier BV, 2014-11)[Article]
The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex's folded pattern for ultra-compact design.
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