Arsalan, Muhammad; Ouda, Mahmoud H.; Marnat, Loic; Shamim, Atif; Salama, Khaled N.(2013 IEEE MTT-S International Microwave Workshop Series on RF and Wireless Technologies for Biomedical and Healthcare Applications (IMWS-BIO), Institute of Electrical and Electronics Engineers (IEEE), 2013-12)[Conference Paper]
Ghaffar, Farhan A.; Arsalan, Muhammad; Cheema, Hammad; Salama, Khaled N.; Shamim, Atif(The 8th European Conference on Antennas and Propagation (EuCAP 2014), Institute of Electrical and Electronics Engineers (IEEE), 2014-04)[Conference Paper]
A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.
Cheema, Hammad M.; Arsalan, Muhammad; Salama, Khaled N.; Shamim, Atif(Microwave and Optical Technology Letters, Wiley-Blackwell, 2015-01-23)[Article]
A 60-GHz fundamental frequency phase locked loop (PLL) as part of a highly integrated system-on-chip transmitter with onchip memory and antenna is presented. As a result of localized optimization approach for each component, the PLL core components only consume 30.2 mW from a 1.2 V supply. A systematic design procedure to achieve high phase margin and wide locking range is presented. The reduction of parasitic and fixed capacitance contributions in the voltage controlled oscillator enables the coverage of the complete 802.11 ad frequency band from 57.2 to 65.8 GHz. A new 4-stage distribution network supplying the local oscillator (LO) signal to the mixer, the feedback loop and the external equipment is introduced. The prescaler based on the static frequency division approach is enhanced using shunt-peaking and asymmetric capacitive loading. The current mode logic based divider chain is optimized for low power and minimum silicon foot-print. A dead-zone free phase frequency detector, low leakage charge pump, and an integrated second-order passive filter completes the feedback loop. The PLL implemented in 65 nm CMOS process occupies only 0.6 mm2 of chip space and has a measured locking range from 56.8 to 66.5 GHz. The reference spurs are lower than -40 dBc and the in-band and out-of-band phase noise is -88.12 dBc/Hz and -117 dBc/Hz, respectively.
Radwan, Ahmed Gomaa; Shamim, Atif; Salama, Khaled N.(Proceedings of the 2012 IEEE International Symposium on Antennas and Propagation, Institute of Electrical and Electronics Engineers (IEEE), 2012-07)[Conference Paper]
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