• 24-GHz LTCC Fractal Antenna Array SoP With Integrated Fresnel Lens

      Ghaffar, Farhan A.; Khalid, Muhammad Umair; Salama, Khaled N.; Shamim, Atif (Institute of Electrical and Electronics Engineers (IEEE), 2012-09-30)
      A novel 24-GHz mixed low-temperature co-fired ceramic (LTCC) tape based system-on-package (SoP) is presented, which incorporates a fractal antenna array with an integrated grooved Fresnel lens. The four-element fractal array employs a relatively low dielectric constant substrate (CT707, εr = 6.4), whereas the lens has been realized on a high-dielectric-constant superstrate (CT765, εr = 68.7 ). The two (substrate and superstrate) are integrated through four corner posts to realize the required air gap (focal distance). The fractal array alone provides a measured gain of 8.9 dBi. Simulations predict that integration of this array with the lens increases the gain by 6 dB. Measurements reveal that the design is susceptible to LTCC fabrication tolerances. In addition to high gain, the SoP provides a bandwidth of 8%. The high performance and compact size (24 × 24 × 4.8 mm3 ) of the design makes it highly suitable for emerging wireless applications such as automotive radar front end.
    • 5.2-GHz RF Power Harvester in 0.18-/spl mu/m CMOS for Implantable Intraocular Pressure Monitoring

      Ouda, Mahmoud H.; Arsalan, Muhammad; Marnat, Loic; Salama, Khaled N.; Shamim, Atif (Institute of Electrical and Electronics Engineers (IEEE), 2013-04-17)
      A first fully integrated 5.2-GHz CMOS-based RF power harvester with an on-chip antenna is presented in this paper. The design is optimized for sensors implanted inside the eye to wirelessly monitor the intraocular pressure of glaucoma patients. It includes a five-stage RF rectifier with an on-chip antenna, a dc voltage limiter, two voltage sensors, a low dropout voltage regulator, and MOSCAP based on-chip storage. The chip has been designed and fabricated in a standard 0.18-μm CMOS technology. To emulate the eye environment in measurements, a custom test setup is developed that comprises Plexiglass cavities filled with saline solution. Measurements in this setup show that the proposed chip can be charged to 1 V wirelessly from a 5-W transmitter 3 cm away from the harvester chip. The energy that is stored on the 5-nF on-chip MOSCAP when charged to 1 V is 2.5 nJ, which is sufficient to drive an arbitrary 100-μW load for 9 μs at regulated 0.8 V. Simulated efficiency of the rectifier is 42% at -7 dBm of input power.
    • A 5.2GHz, 0.5mW RF powered wireless sensor with dual on-chip antennas for implantable intraocular pressure monitoring

      Arsalan, Muhammad; Ouda, Mahmoud H.; Marnat, Loic; Ahmad, Talha Jamal; Shamim, Atif; Salama, Khaled N. (Institute of Electrical and Electronics Engineers (IEEE), 2013-06)
      For the first time a single chip implantable wireless sensor system for Intraocular Pressure Monitoring (IOPM) is presented. This system-on-chip (SoC) is battery-free and harvests energy from incoming RF signals. The chip is self-contained and does not require external components or bond wires to function. This 1.4mm3 SoC has separate 2.4GHz-transmit and 5.2GHz-receive antennas, an energy harvesting module, a temperature sensor, a 7-bit TIQ Flash ADC, a 4-bit RFID, a power management and control unit, and a VCO transmitter. The chip is fabricated in a standard 6-metal 0.18μm CMOS process and is designed to work with a post-processed MEMS pressure sensor. It consumes 513μW of peak power and when implanted inside the eye, it is designed to communicate with an external reader using on-off keying (OOK). © 2013 IEEE.
    • 50V All-PMOS Charge Pumps Using Low-Voltage Capacitors

      Emira, Ahmed; AbdelGhany, M.; Elsayed, M.; Elshurafa, Amro M.; Sedky, S.; Salama, Khaled N. (Institute of Electrical and Electronics Engineers (IEEE), 2012-10-06)
      In this work, two high-voltage charge pumps are introduced. In order to minimize the area of the pumping capacitors, which dominates the overall area of the charge pump, high density capacitors have been utilized. Nonetheless, these high density capacitors suffer from low breakdown voltage which is not compatible with the targeted high voltage application. To circumvent the breakdown limitation, a special clocking scheme is used to limit the maximum voltage across any pumping capacitor. The two charge pump circuits were fabricated in a 0:6m CMOS technology with poly0-poly1 capacitors. The output voltage of the two charge pumps reached 42:8V and 51V while the voltage across any capacitor did not exceed the value of the input voltage. Compared to other designs reported in the literature, the proposed charge pump provides the highest output voltage which makes it more suitable for tuning MEMS devices.
    • 60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

      Ghaffar, Farhan A.; Arsalan, Muhammad; Cheema, Hammad; Salama, Khaled N.; Shamim, Atif (Institute of Electrical and Electronics Engineers (IEEE), 2014-04)
      A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.
    • 7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

      Omran, Hesham; Arsalan, Muhammad; Salama, Khaled N. (Institute of Electrical and Electronics Engineers (IEEE), 2014-08)
      In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.
    • ABS: Sequence alignment by scanning

      Bonny, Mohamed Talal; Salama, Khaled N. (Institute of Electrical and Electronics Engineers (IEEE), 2011-08)
      Sequence alignment is an essential tool in almost any computational biology research. It processes large database sequences and considered to be high consumers of computation time. Heuristic algorithms are used to get approximate but fast results. We introduce fast alignment algorithm, called Alignment By Scanning (ABS), to provide an approximate alignment of two DNA sequences. We compare our algorithm with the well-known alignment algorithms, the FASTA (which is heuristic) and the 'Needleman-Wunsch' (which is optimal). The proposed algorithm achieves up to 76% enhancement in alignment score when it is compared with the FASTA Algorithm. The evaluations are conducted using different lengths of DNA sequences. © 2011 IEEE.
    • Achieving nanoscale horizontal separations in the standard 2 μm PolyMUMPS process

      Elshurafa, Amro M.; Salama, Khaled N. (Springer Science + Business Media, 2013-01-25)
      This paper shares with the research community how to achieve, effectively and easily, lateral submicron separations in the standard 2 lm PolyMUMPS process without any fabrication intervention or post-processing, based on the oxide sidewall spacer technique. Thousands of nanoseparations were created and successfully tested by visual inspection and by a simple capacitance measurement. The lateral separations attained were less than 440 nm and reached as low as 280 nm. To corroborate the findings, measurements were performed on different capacitors fabricated in different fabrication runs with consistent results. This is the first time that submicron lateral distances are reported in PolyMUMPS using the oxide spacer technique.
    • An acoustic system for autonomous navigation and tracking of marine fauna

      De la Torre, Pedro; Salama, Khaled N.; Berumen, Michael L. (Institute of Electrical and Electronics Engineers (IEEE), 2014-08)
      A marine acoustic system for underwater target tracking is described. This system is part of the Integrated Satellite and Acoustic Telemetry (iSAT) project to study marine fauna. It is a microcontroller-based underwater projector and receiver. A narrow-band, passive sonar detection architecture is described from signal generation, through transduction, reception, signal processing and up to tone extraction. Its circuit and operation principles are described. Finally, a comparison between the current energy detection method versus an alternative matched filter approach is included.
    • An Adaptive Hybrid Multiprocessor technique for bioinformatics sequence alignment

      Bonny, Talal; Salama, Khaled N.; Zidan, Mohammed A. (Institute of Electrical and Electronics Engineers (IEEE), 2012-07-28)
      Sequence alignment algorithms such as the Smith-Waterman algorithm are among the most important applications in the development of bioinformatics. Sequence alignment algorithms must process large amounts of data which may take a long time. Here, we introduce our Adaptive Hybrid Multiprocessor technique to accelerate the implementation of the Smith-Waterman algorithm. Our technique utilizes both the graphics processing unit (GPU) and the central processing unit (CPU). It adapts to the implementation according to the number of CPUs given as input by efficiently distributing the workload between the processing units. Using existing resources (GPU and CPU) in an efficient way is a novel approach. The peak performance achieved for the platforms GPU + CPU, GPU + 2CPUs, and GPU + 3CPUs is 10.4 GCUPS, 13.7 GCUPS, and 18.6 GCUPS, respectively (with the query length of 511 amino acid). © 2010 IEEE.
    • Adaptive Processing for Sequence Alignment

      Zidan, Mohammed A.; Bonny, Talal; Salama, Khaled N. (2012-01-26)
      Disclosed are various embodiments for adaptive processing for sequence alignment. In one embodiment, among others, a method includes obtaining a query sequence and a plurality of database sequences. A first portion of the plurality of database sequences is distributed to a central processing unit (CPU) and a second portion of the plurality of database sequences is distributed to a graphical processing unit (GPU) based upon a predetermined splitting ratio associated with the plurality of database sequences, where the database sequences of the first portion are shorter than the database sequences of the second portion. A first alignment score for the query sequence is determined with the CPU based upon the first portion of the plurality of database sequences and a second alignment score for the query sequence is determined with the GPU based upon the second portion of the plurality of database sequences.
    • Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

      Hanna, Amir; Hussain, Aftab M.; Omran, Hesham; Alshareef, Sarah; Salama, Khaled N.; Hussain, Muhammad Mustafa (Institute of Electrical and Electronics Engineers (IEEE), 2015-12-04)
      High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.
    • Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator

      Mansingka, Abhinav S.; Radwan, Ahmed G.; Salama, Khaled N.; Zidan, Mohammed A. (Institute of Electrical and Electronics Engineers (IEEE), 2012-07-29)
      This paper introduces the first fully digital implementation of a 3rd order ODE-based chaotic oscillator with signum nonlinearity. A threshold bus width of 12-bits for reliable chaotic behavior is observed, below which the system output becomes periodic. Beyond this threshold, the maximum Lyapunov exponent (MLE) is shown to improve up to a peak value at 16-bits and subsequently decrease with increasing bus width. The MLE is also shown to gradually increase with number of introduced internal delay cycles until a peak value at 14 cycles, after which the system loses chaotic properties. Introduced external delay cycles are shown to rotate the attractors in 3-D phase space. Bus width and delay elements can be independently modulated to optimize the system to suit specifications. The experimental results of the system show low area and high performance on a Xilinx Virtex 4 FPGA with throughput of 13.35 Gbits/s for a 32-bit implementation.
    • Architectural optimizations for low-power K-best MIMO decoders

      Mondal, Sudip; Eltawil, Ahmed M.; Salama, Khaled N. (Institute of Electrical and Electronics Engineers (IEEE), 2009-09)
      Maximum-likelihood (ML) detection for higher order multiple-input-multiple-output (MIMO) systems faces a major challenge in computational complexity. This limits the practicality of these systems from an implementation point of view, particularly for mobile battery-operated devices. In this paper, we propose a modified approach for MIMO detection, which takes advantage of the quadratic-amplitude modulation (QAM) constellation structure to accelerate the detection procedure. This approach achieves low-power operation by extending the minimum number of paths and reducing the number of required computations for each path extension, which results in an order-of-magnitude reduction in computations in comparison with existing algorithms. This paper also describes the very-large-scale integration (VLSI) design of the low-power path metric computation unit. The approach is applied to a 4 × 4, 64-QAM MIMO detector system. Results show negligible performance degradation compared with conventional algorithms while reducing the complexity by more than 50%. © 2009 IEEE.
    • A best-first soft/hard decision tree searching MIMO decoder for a 4 × 4 64-QAM system

      Shen, Chungan; Eltawil, Ahmed M.; Salama, Khaled N.; Mondal, Sudip (Institute of Electrical and Electronics Engineers (IEEE), 2012-08)
      This paper presents the algorithm and VLSI architecture of a configurable tree-searching approach that combines the features of classical depth-first and breadth-first methods. Based on this approach, techniques to reduce complexity while providing both hard and soft outputs decoding are presented. Furthermore, a single programmable parameter allows the user to tradeoff throughput versus BER performance. The proposed multiple-input-multiple-output decoder supports a 4 × 4 64-QAM system and was synthesized with 65-nm CMOS technology at 333 MHz clock frequency. For the hard output scheme the design can achieve an average throughput of 257.8 Mbps at 24 dB signal-to-noise ratio (SNR) with area equivalent to 54.2 Kgates and a power consumption of 7.26 mW. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW. © 2011 IEEE.
    • A best-first tree-searching approach for ML decoding in MIMO system

      Shen, Chung-An; Eltawil, Ahmed M.; Mondal, Sudip; Salama, Khaled N. (Institute of Electrical and Electronics Engineers (IEEE), 2012-07-28)
      In MIMO communication systems maximum-likelihood (ML) decoding can be formulated as a tree-searching problem. This paper presents a tree-searching approach that combines the features of classical depth-first and breadth-first approaches to achieve close to ML performance while minimizing the number of visited nodes. A detailed outline of the algorithm is given, including the required storage. The effects of storage size on BER performance and complexity in terms of search space are also studied. Our result demonstrates that with a proper choice of storage size the proposed method visits 40% fewer nodes than a sphere decoding algorithm at signal to noise ratio (SNR) = 20dB and by an order of magnitude at 0 dB SNR.
    • Bio-Inspired Carbon Monoxide Sensors with Voltage-Activated Sensitivity

      Savagatrup, Suchol; Schroeder, Vera; He, Xin; Lin, Sibo; He, Maggie; Yassine, Omar; Salama, Khaled N.; Zhang, Xixiang; Swager, Timothy M. (Wiley-Blackwell, 2017-09-27)
      Carbon monoxide (CO) outcompetes oxygen when binding to the iron center of hemeproteins, leading to a reduction in blood oxygen level and acute poisoning. Harvesting the strong specific interaction between CO and the iron porphyrin provides a highly selective and customizable sensor. We report the development of chemiresistive sensors with voltage-activated sensitivity for the detection of CO comprising iron porphyrin and functionalized single-walled carbon nanotubes (F-SWCNTs). Modulation of the gate voltage offers a predicted extra dimension for sensing. Specifically, the sensors show a significant increase in sensitivity toward CO when negative gate voltage is applied. The dosimetric sensors are selective to ppm levels of CO and functional in air. UV/Vis spectroscopy, differential pulse voltammetry, and density functional theory reveal that the in situ reduction of FeIII to FeII enhances the interaction between the F-SWCNTs and CO. Our results illustrate a new mode of sensors wherein redox active recognition units are voltage-activated to give enhanced and highly specific responses.
    • Biosensor for the detection of Listeria monocytogenes: emerging trends

      Soni, Dharmendra Kumar; Ahmad, Rafiq; Dubey, Suresh Kumar (Informa UK Limited, 2018-05-23)
      The early detection of Listeria monocytogenes (L. monocytogenes) and understanding the disease burden is of paramount interest. The failure to detect pathogenic bacteria in the food industry may have terrible consequences, and poses deleterious effects on human health. Therefore, integration of methods to detect and trace the route of pathogens along the entire food supply network might facilitate elucidation of the main contamination sources. Recent research interest has been oriented towards the development of rapid and affordable pathogen detection tools/techniques. An innovative and new approach like biosensors has been quite promising in revealing the foodborne pathogens. In spite of the existing knowledge, advanced research is still needed to substantiate the expeditious nature and sensitivity of biosensors for rapid and in situ analysis of foodborne pathogens. This review summarizes recent developments in optical, piezoelectric, cell-based, and electrochemical biosensors for Listeria sp. detection in clinical diagnostics, food analysis, and environmental monitoring, and also lists their drawbacks and advantages.
    • Capacitive immunosensor for C-reactive protein quantification

      Sapsanis, Christos; Sivashankar, Shilpa; Omran, Hesham; Buttner, Ulrich; Salama, Khaled N. (Institute of Electrical and Electronics Engineers (IEEE), 2015-08-02)
      We report an agglutination-based immunosensor for the quantification of C-reactive protein (CRP). The developed immunoassay sensor requires approximately 15 minutes of assay time per sample and provides a sensitivity of 0.5 mg/L. We have measured the capacitance of interdigitated electrodes (IDEs) and quantified the concentration of added analyte. The proposed method is a label free detection method and hence provides rapid measurement preferable in diagnostics. We have so far been able to quantify the concentration to as low as 0.5 mg/L and as high as 10 mg/L. By quantifying CRP in serum, we can assess whether patients are prone to cardiac diseases and monitor the risk associated with such diseases. The sensor is a simple low cost structure and it can be a promising device for rapid and sensitive detection of disease markers at the point-of-care stage.
    • Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

      Shamim, Atif; Arsalan, Muhammad; Roy, L; Salama, Khaled N. (Institute of Electrical and Electronics Engineers (IEEE), 2012-07-28)
      The surge of highly integrated and multifunction wireless devices has necessitated the designers to think outside the box for solutions that are unconventional. The new trends have provided the impetus for low cost and compact RF System-on-Chip (SoC) approaches [1]. The major advantages of SoC are miniaturization and cost reduction. A major bottleneck to the true realization of monolithic RF SoC transceivers is the implementation of on-chip antennas with circuitry. Though complete integrated transceivers with on-chip antennas have been demonstrated, these designs are generally for high frequencies. Moreover, they either use non-standard CMOS processes or additional fabrication steps to enhance the antenna efficiency, which in turn adds to the cost of the system [2-3]. Another challenge related to the on-chip antennas is the characterization of their radiation properties. Most of the recently reported work (summarized in Table I) shows that very few on-chip antennas are characterized. Our previous work [4], demonstrated a Phase Lock Loop (PLL) based transmitter (TX) with an on-chip antenna. However, the radiation from the on-chip antenna experienced strong interference due to 1) some active circuitry on one side of the chip and 2) the PCB used to mount the chip in the anechoic chamber. This paper presents, for the first time, a complete 5.2 GHz (UNII band) transceiver with separate TX and receiver (RX) antennas. To the author's best knowledge, its size of 3 mm2 is the smallest reported for a UNII band transceiver with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been discussed. © 2010 IEEE.